GBE-PCS-PM-U1 查看數據表（PDF） - Lattice Semiconductor

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GBE-PCS-PM-U1

Gigabit Ethernet PCS IP Core for LatticeECP2M

Lattice Semiconductor 

Lattice Semiconductor

Gigabit Ethernet PCS IP Core

for LatticeECP2M

Introduction

The 1000BASE-X physical layer, also referred to as the Gigabit Ethernet (GbE) physical layer, consists of three

major blocks, the Physical Coding Sublayer (PCS), the Physical Medium Attachment sublayer (PMA), and the

Physical Medium Dependent sublayer (PMD). The LatticeECP2M™ embedded SERDES/PCS performs the PMA

function, and portions of the PMD and PCS functions, including link serialization/deserialization, code-group align-

ment, clock tolerance compensation buffering, and 8b10b encoding/decoding. However, the embedded SER-

DES/PCS does not provide all necessary functions for implementing a complete GbE physical layer solution. That’s

where the GbE PCS IP core comes in. The IP core provides the additional functions required to fully implement the

PCS functions of the GbE physical layer. These additional functions include a transmit state machine, a receive

state machine, and auto-negotiation.

This document describes the IP core’s operation and provides instructions for generating the core through

ispLEVER® IPexpress™, including instantiating, synthesizing, and simulating the core.

Features

• Implements the transmit, receive, and auto-negotiation functions of the IEEE 802.3z specification

• 8-bit GMII Interface operating at 125 MHz

• 8-bit Code-Group Interface operating at 125 MHz

• Parallel signal interface for control and status management

Functional Description

The GbE PCS IP core converts GMII data frames into 8-bit code groups in both transmit and receive directions;

and performs auto negotiation with a link partner as described in the IEEE 802.3z specification. The core’s block

diagram is shown in Figure 1. The following paragraphs detail the operation the IP core’s main functional blocks. An

example of how this IP core may be used in implementing a gigabit ethernet physical layer is shown in Figure 2.

Figure 1. GbE PCS IP Core Block Diagram

GMII Interface

MAC/PHY Mode

mr_adv_ability

mr_an_enable

mr_main_reset

mr_restart_an

Transmit

State Machine

Auto-Negotiation

State Machine

Receive

State Machine

Synchronization

State Machine

mr_an_complete

mr_lp_adv_ability

mr_page_rx

8-bit Code Group Interface

2

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