82433NX 查看數據表（PDF） - Intel
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82433NX Datasheet PDF : 53 Pages
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82433LX 82433NX
Order Pin
79 104
80 105
81 106
82 107
83 108
84 109
85 112
86 113
87 114
88 115
89 116
90 117
91 118
82 119
93 123
Table 9 NAND Tree Sequence (Continued)
Signal
Non-
Inverting
MD6
N
MD22
N
MD15
N
MD31
N
MD7
N
MD23
N
MP0
N
MP2
N
MP1
N
MP3
N
AD0
Y
AD1
Y
AD2
Y
AD3
Y
EOL
Y
Order Pin
94 125
95 126
96 127
97 128
98 129
99 131
100 132
101 133
102 134
103 135
104 136
105 137
106 138
107 143
Signal
Non-
Inverting
AD4
Y
AD5
Y
AD6
Y
AD7
Y
AD8
Y
AD9
Y
AD10
Y
AD11
Y
AD12
Y
AD13
Y
AD14
Y
AD15
Y
MDLE
Y
DRVPCI N
Order Pin
108 144
109 145
110 146
111 147
112 148
113 151
114 152
115 153
116 154
117 155
118 156
119 157
120 158
121 159
Signal
Non-
Inverting
PIG3
N
PIG2
N
PIG1
N
PIG0
N
D7
Y
HP0
Y
D8
Y
D1
Y
D5
Y
D3
Y
D10
Y
D15
Y
D13
Y
D9
Y
6 2 PLL Test Mode
The high order 82433NX LBX samples A11 at the
falling edge of reset to configure the LBX for PLL
test mode When A11 is sampled low the LBX is in
normal operating mode When A11 is sampled high
the LBX drives the internal HCLK from the PLL on
the EOL pin
53
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