STM8AP528A 查看數據表（PDF） - STMicroelectronics
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STM8AP528A Datasheet PDF : 125 Pages
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Product overview
5
Product overview
STM8AF526x/8x/Ax STM8AF6269/8x/Ax
5.1
5.1.1
5.1.2
5.1.3
This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to STM8S series and STM8AF
series 8-bit microcontrollers reference manual (RM0016).
STM8A central processing unit (CPU)
The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each
execution context), 20 addressing modes including indexed indirect and relative addressing
and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus with single cycle fetching for most instructions
• X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter with 16-Mbyte linear memory space
• 16-bit stack pointer with access to a 64 Kbyte stack
• 8-bit condition code register with seven condition flags for the result of the last
instruction.
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up tables located anywhere in the address
space
• Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
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