MAX1203ACAP-T 查看數據表（PDF） - Maxim Integrated

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MAX1203ACAP-T

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

Simple Software Interface

Make sure the CPU’s serial interface runs in master mode

so the CPU generates the serial clock. Choose a clock

frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and

call it TB1. TB1’s format should be: 1XXXXX11 binary,

where the Xs denote the particular channel and con-

version mode selected.

2) Use a general-purpose I/O line on the CPU to pull CS

on the MAX1202/MAX1203 low.

3) Transmit TB1 and simultaneously receive a byte and

call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and simultane-

ously receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and simultane-

ously receive byte RB3.

6) Pull CS on the MAX1202/MAX1203 high.

Figure 6 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion padded with

one leading zero and three trailing zeros. The total con-

version time is a function of the serial-clock frequency and

the amount of idle time between 8-bit transfers. To avoid

excessive T/H droop, make sure that the total conversion

time does not exceed 120μs.

Digital Output

In unipolar-input mode, the output is straight binary

(Figure 15); for bipolar inputs, the output is two’s comple-

ment (Figure 16). Data is clocked out at SCLK’s falling

edge in MSB-first format. The digital output logic level is

adjusted with the VL pin. This allows DOUT and SSTRB

to interface with 3V logic without the risk of overdrive. The

MAX1202/MAX1203’s digital inputs are designed to be

compatible with 5V CMOS logic as well as 3V logic.

Internal and External Clock Modes

The MAX1202/MAX1203 can use either an external serial

clock or the internal clock to perform the successive-

approximation conversion. In both clock modes, the

external clock shifts data in and out of the MAX1202/

MAX1203. The T/H acquires the input signal as the last

three bits of the control byte are clocked into DIN. Bits

PD1 and PD0 of the control byte program the clock mode.

Figures 7–10 show the timing characteristics common to

both modes.

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the A/D conversion

steps. SSTRB pulses high for one clock period after the

last bit of the control byte. Successive-approximation bit

decisions are made and appear at DOUT on each of the

next 12 SCLK falling edges (Figure 6). SSTRB and DOUT

go into a high-impedance state when CS goes high; after

CS

SCLK

1

tACQ

4

8

DIN

SSTRB

DOUT

ADC STATE

SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

START

RB1

ACQUISITION

IDLE

1.5µs

(SCLK = 2MHz)

12

16

20

24

RB2

RB3

B11

MSB

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

LSB

FILLED WITH

ZEROS

CONVERSION

IDLE

Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)

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