171020601 查看數據表（PDF） - Wurth Elektronik GmbH & Co. KG, Germany.

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171020601

MagI3C Power Module VDRM – Variable Step Down Regulator Module

Wurth Elektronik GmbH & Co. KG, Germany. 

WPMDM1500602 / 171050601

MagI3C Power Module

VDRM – Variable Step Down Regulator Module

Step 2 Select the input capacitor (CIN)

The MagI³C power module internally contains two ceramic capacitors of 0.47µF each. The module requires additional,

external input capacitance to handle the input current ripple. This input capacitance should be located as close as possible

to the MagI³C power module. Input capacitor selection is generally based on different requirements. The first criterion is the

input current ripple. Worst case input current ripple rating is dictated by the equation:

ICINRMS

≈

1

2

∙

IOUT

∙

√D

1-D

(2)

where D≈ VOUT

VIN

As a point of reference, the worst case current ripple will occur when the module is presented with full load current and when

VIN = 2 x VOUT.

Recommended minimum input capacitance is 22µF (including derating) ceramic with a voltage rating at least 25% higher

than the maximum applied input voltage for the application. It is strongly recommended to pay attention to the voltage and

temperature deratings of the capacitor selected. It should be noted that current ripple rating of ceramic capacitors may be

missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.

The second criterion is the input voltage ripple.

If the system design requires a certain minimum value of peak-to-peak input voltage ripple (VIN ripple) then the following

equation may be used:

CIN≥

fSW(CCM)

IOUT ∙

∙ (VIN

D ∙ (1 − D)

ripple − ESR∙IOUT∙D)

(3)

The duty cycle is theoretically defined as the ratio between the output and the input voltage. In reality, the efficiency should

also be taken into consideration when calculating the duty cycle, as shown by the following formula:

D=

VOUT

VIN ∙ ��

(4)

where �� represents the efficiency and its value under the specified conditions can be found in the “Efficiency” section on

page 10.

As example, if ΔVIN ≤ 100mV for a 12V input to 5V output application, IOUT = 5A, reading the efficiency from the diagram on

page 10 (85%) and assuming ESR = 5mΩ, this leads to:

CIN

≥

5A∙

5V

12V∙0.85

∙(1–

5V

12V∙0.85

)

812000Hz∙0.1V

CIN ≥ 17.5µF

Additional bulk capacitance with higher ESR may be required to damp any resonant effects between the input capacitance

and parasitic inductance of the incoming supply lines.

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© July 2018

Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 2.0

19/56

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