WPMDM1500602 / 171050601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Selection by load step requirements
The output voltage is also affected by load transients (see picture below).
When the output current transitions from a low to a high value, the voltage at the output capacitor (VOUT) drops. This involves
two contributing factors. One is caused by the voltage drop across the ESR (VESR) and depends on the slope of the rising
edge of the current step (trise). For low ESR values and small load currents, this is often negligible. It can be calculated as
follows:
VESR=ESR∙∆IOUT
(10)
where ∆IOUT is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
IOUT
0
VOUT
trise
VESR
Vdi sch arge
∆IOUT
t
∆VOUT
0
t
td
treg
The second contributing factor is the voltage drop due to discharge of the output capacitor, which can be estimated as:
Vdischarge=
∆IOUT∙td
2∙COUT
(11)
In a current mode architecture the td is strictly related to the bandwidth of the regulation loop and influenced by the COUT (if
COUT increases, the td increases as well).
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© July 2018
Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 2.0
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