MAX3396E 查看數據表（PDF） - Maxim Integrated
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MAX3396E Datasheet PDF : 20 Pages
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±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
VL
VCC
VL
VCC
EN
MAX3394E
MAX3395E
VL MAX3396E
VCC
RLOAD RLOAD
VL
VCC
VL
EN
VL
VCC
MAX3394E
MAX3395E
MAX3396E
VCC
I/O VL_
50Ω
I/O VCC_
CIOVCC
I/O VL_
CIOVL
I/O VCC_
50Ω
tEN
V
I/O VCC_
EN
0.5V
TIME
V
tEN
I/O VL_
EN
0.2V (VL < 2V)
0.5V (VL ≥ 2V)
Figure 5. Enable Test Circuit and Timing
Power-Supply Sequencing
The MAX3394E/MAX3395E/MAX3396E require two sup-
ply voltages. For proper operation, ensure that +1.65V ≤
VCC ≤ +5.5V, and +1.2V ≤ VL ≤ VCC. There are no restric-
tions on power-supply sequencing. During power-up or
power-down, the MAX3394E/MAX3395E/MAX3396E can
withstand either the VL or the VCC supply floating while
the other supply is applied. The device will not latch up in
this state.
TIME
Tri-State Output Mode
Connect EN to VL or VCC for normal operation. Drive
EN low to force the MAX3394E/MAX3395E/MAX3396E
to a tri-state output mode. In tri-state output mode, all
I/O lines are driven to a high-impedance state, and the
pass-FET is disabled to prevent current flow between
I/O lines. Tri-state output mode disables the internal
pullup resistors on I/O VL_ and I/O VCC_, and reduces
supply current to 3µA typ (VCC) and 0.7µA typ (VL).
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