MAX3395E 查看數據表（PDF） - Maxim Integrated

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MAX3395E

±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry

Maxim Integrated 

±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/

Octal-Level Translators with Speed-Up Circuitry

MAX3394E

TDFN UCSP

1

A1

2

B1

3

A2

4

A3

5

B3

6

C3

7

C2

8

C1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

EP

—

PIN

MAX3395E

TQFN UCSP

11

B1

6

B3

10

C1

9

C2

5

B4

2

A2

1

A1

12

B2

3

A3

4

A4

7

C4

8

C3

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

EP

—

Pin Description

MAX3396E

TQFN UCSP

14

D3

4

A4

18

C1

16

D1

13

D4

20

A1

19

B1

3

A3

1

B2

2

A2

15

D2

17

C2

12

C3

11

D5

10

C4

9

C5

5

B3

6

A5

7

B4

8

B5

EP

—

NAME

FUNCTION

VCC Supply Voltage +1.65V ≤ VCC ≤ +5.5V. Bypass

VCC

VCC to GND with a 0.1µF ceramic capacitor and a

1µF or greater ceramic capacitor as close to the

device as possible.

Enable Input. Drive EN logic high for normal

EN

operation. Drive EN logic low to force all I/O lines to

a high-impedance state and disconnect internal

pullup resistors.

I/O VCC1

I/O VCC2

GND

I/O VL2

I/O VL1

I/O 1 Referred to VCC

I/O 2 Referred to VCC

Ground

I/O 2 Referred to VL

I/O 1 Referred to VL

Logic Supply Voltage +1.2V ≤ VL ≤ VCC. Bypass VL

VL

to GND with a 0.1µF or greater ceramic capacitor

as close to the device as possible.

I/O VL3

I/O VL4

I/O VCC4

I/O VCC3

I/O VCC5

I/O VCC6

I/O VCC7

I/O VCC8

I/O VL5

I/O VL6

I/O VL7

I/O VL8

EP

I/O 3 Referred to VL

I/O 4 Referred to VL

I/O 4 Referred to VCC

I/O 3 Referred to VCC

I/O 5 Referred to VCC

I/O 6 Referred to VCC

I/O 7 Referred to VCC

I/O 8 Referred to VCC

I/O 5 Referred to VL

I/O 6 Referred to VL

I/O 7 Referred to VL

I/O 8 Referred to VL

Exposed Pad. Connect exposed pad to GND.

Detailed Description

The MAX3394E/MAX3395E/MAX3396E bidirectional

level translators provide level shifting required for data

transfer in a multivoltage system. Internal slew-rate

enhancement circuitry features 10mA current-sink and

15mA current-source drivers to isolate capacitive loads

from lower current drivers. In open-drain systems, slew-

rate enhancement enables fast data rates with larger

pullup resistors and increased bus load capacitance.

Externally applied voltages, VCC and VL, set the logic-

high levels for the device. A logic-low signal on one I/O

side of the device appears as a logic-low signal on the

opposite I/O side and vice-versa. Each I/O line is pulled

up to VCC or VL by an internal pullup resistor, allowing

the devices to be driven by either push-pull or open-

drain drivers.

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