MAX3395E 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
生产厂家
MAX3395E Datasheet PDF : 20 Pages
| |||
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
VL
I/O VL_
50Ω
VL EN
MAX3394E
MAX3395E
VL MAX3396E
VCC
VCC
tRVCC
90%
I/O VL
VCC
50%
50%
I/O VCC_
CIOVCC
I/O VCC 10%
tFVCC
90%
50%
50%
10%
Figure 1. Push-Pull Driving I/O VL_ Test Circuit and Timing
tI/OVL-VCC
tI/OVL-VCC
VL
VCC
VL EN
VCC
MAX3394E
MAX3395E
VL MAX3396E
VCC
I/O VL_
VGATE
I/O VCC_
CIOVCC
VGATE
50%
10%
tRVCC
90%
I/O VCC
tFVCC
90%
50%
50%
50%
10%
tI/OVL-VCC
tI/OVL-VCC
Figure 2. Open-Drain Driving I/O VL_ Test Circuit and Timing
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on
the VCC side for greater protection in applications that
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept VCC volt-
ages from +1.65V to +5.5V, and VL voltages from +1.2V
to VCC, making them ideal for data transfer between low-
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396E operate at a guaran-
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
Level Translation
The MAX3394E/MAX3395E/MAX3396E utilize a trans-
mission gate architecture to provide bidirectional level
translation between I/O VL_ and I/O VCC_. The trans-
mission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuit-
ry. When both I/O VL_ and I/O VCC_ are logic high, the
gate-control logic disables the pass-FET, providing
8 _______________________________________________________________________________________
Share Link: 