EP2S130F1020C3 查看數據表（PDF） - Unspecified

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EP2S130F1020C3

Stratix II Device Handbook, Volume 1

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Stratix II Architecture

The number of M512 RAM, M4K RAM, and DSP blocks varies by device

along with row and column numbers and M-RAM blocks. Table 2–1 lists

the resources available in Stratix II devices.

Table 2–1. Stratix II Device Resources

Device

EP2S15

EP2S30

EP2S60

EP2S90

EP2S130

EP2S180

M512 RAM

Columns/Blocks

4 / 104

6 / 202

7 / 329

8 / 488

9 / 699

11 / 930

M4K RAM

Columns/Blocks

3 / 78

4 / 144

5 / 255

6 / 408

7 / 609

8 / 768

M-RAM

Blocks

0

1

2

4

6

9

DSP Block

Columns/Blocks

2 / 12

2 / 16

3 / 36

3 / 48

3 / 63

4 / 96

LAB

Columns

LAB Rows

30

26

49

36

62

51

71

68

81

87

100

96

Logic Array

Blocks

Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,

LAB control signals, local interconnect, and register chain connection

lines. The local interconnect transfers signals between ALMs in the same

LAB. Register chain connections transfer the output of an ALM register to

the adjacent ALM register in an LAB. The Quartus® II Compiler places

associated logic in an LAB or adjacent LABs, allowing the use of local,

shared arithmetic chain, and register chain connections for performance

and area efficiency. Figure 2–2 shows the Stratix II LAB structure.

Altera Corporation

May 2007

2–3

Stratix II Device Handbook, Volume 1

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