LFE3-150EA-7MG328I 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

LFE3-150EA-7MG328I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

Table 2-5. DLL Signals

Signal

I/O

CLKI

I

CLKFB

I

RSTN

I

ALUHOLD

I

UDDCNTL

I

CLKOP

O

CLKOS

O

LOCK

O

INCI

I

GRAYI[5:0]

I

DIFF

O

INCO

O

GRAYO[5:0]

O

Description

Clock input from external pin or routing

DLL feed input from DLL output, clock net, routing or external pin

Active low synchronous reset

Active high freezes the ALU

Synchronous enable signal (hold high for two cycles) from routing

The primary clock output

The secondary clock output with fine delay shift and/or division by 2 or by 4

Active high phase lock indicator

Incremental indicator from another DLL via CIB.

Gray-coded digital control bus from another DLL in time reference mode.

Difference indicator when DCNTL is difference than the internal setting and update is needed.

Incremental indicator to other DLLs via CIB.

Gray-coded digital control bus to other DLLs via CIB

LatticeECP3 devices have two general DLLs and four Slave Delay lines, two per DLL. The DLLs are in the lowest

EBR row and located adjacent to the EBR. Each DLL replaces one EBR block. One Slave Delay line is placed adja-

cent to the DLL and the duplicate Slave Delay line (in Figure 2-6) for the DLL is placed in the I/O ring between

Banks 6 and 7 and Banks 2 and 3.

The outputs from the DLL and Slave Delay lines are fed to the clock distribution network.

For more information, please see TN1178, LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide.

Figure 2-6. Top-Level Block Diagram, High-Speed DLL and Slave Delay Line

HOLD

GRAY_IN[5:0]

INC_IN

RSTN

GSRN

UDDCNTL

DCPS[5:0]

TPIO0 (L) OR TPIO1 (R)

GPLL_PIO

CIB (DATA)

CIB (CLK)

GDLL_PIO

Top ECLK1 (L) OR Top ECLK2 (R)

FB CIB (CLK)

Internal from CLKOP

GDLLFB_PIO

ECLK1

4

3 CLKI

2

1

0

4

3

CLKFB

2

1

0

LatticeECP3

High-Speed DLL

CLKOP

CLKOS

LOCK

GRAY_OUT[5:0]

INC_OUT

DIFF

DCNTL[5:0]*

4

3

CLKI

2

1

0

DCNTL[5:0]

Slave Delay Line

CLKO (to edge clock

muxes as CLKINDEL)

* This signal is not user accessible. It can only be used to feed the slave delay line.

2-9

Share Link: