LFE3-17EA-8LMG328I 查看數據表（PDF） - Lattice Semiconductor

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LFE3-17EA-8LMG328I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Figure 2-8. Clock Divider Connections

Architecture

LatticeECP3 Family Data Sheet

ECLK1

ECLK2

CLKOP (PLL)

CLKOP (DLL)

RST

RELEASE

÷1

÷2

CLKDIV

÷4

÷8

Clock Distribution Network

LatticeECP3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. Two

high performance edge clocks are available on the top, left, and right edges of the device to support high speed

interfaces. These clock sources are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock

sources are fed throughout the chip via a clock distribution system.

Primary Clock Sources

LatticeECP3 devices derive clocks from six primary source types: PLL outputs, DLL outputs, CLKDIV outputs, ded-

icated clock inputs, routing and SERDES Quads. LatticeECP3 devices have two to ten sysCLOCK PLLs and two

DLLs, located on the left and right sides of the device. There are six dedicated clock inputs: two on the top side, two

on the left side and two on the right side of the device. Figures 2-9, 2-10 and 2-11 show the primary clock sources

for LatticeECP3 devices.

Figure 2-9. Primary Clock Sources for LatticeECP3-17

Clock Input Clock Input

From Routing

Clock

Input

Clock

Input

DLL Input

PLL Input

Primary Clock Sources

to Eight Quadrant Clock Selection

CLK

CLK

DIV

DIV

DLL

DLL

PLL

PLL

From Routing

SERDES

Quad

Note: Clock inputs can be configured in differential or single-ended mode.

Clock

Input

Clock

Input

DLL Input

PLL Input

2-11

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