LFE3-70EA-8FN484I 查看數據表（PDF） - Lattice Semiconductor
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LFE3-70EA-8FN484I Datasheet PDF : 140 Pages
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Architecture
LatticeECP3 Family Data Sheet
Secondary Clock/Control Sources
LatticeECP3 devices derive eight secondary clock sources (SC0 through SC7) from six dedicated clock input pads
and the rest from routing. Figure 2-14 shows the secondary clock sources. All eight secondary clock sources are
defined as inputs to a per-region mux SC0-SC7. SC0-SC3 are primary for control signals (CE and/or LSR), and
SC4-SC7 are for the clock.
In an actual implementation, there is some overlap to maximize routability. In addition to SC0-SC3, SC7 is also an
input to the control signals (LSR or CE). SC0-SC2 are also inputs to clocks along with SC4-SC7.
Figure 2-14. Secondary Clock Sources
From From
Routing Routing
Clock
Input
Clock
Input
From From
Routing Routing
From Routing
From Routing
Clock Input
Clock Input
From Routing
From Routing
Secondary Clock Sources
From Routing
From Routing
Clock Input
Clock Input
From Routing
From Routing
From From
Routing Routing
From From
Routing Routing
Note: Clock inputs can be configured in differential or single-ended mode.
Secondary Clock/Control Routing
Global secondary clock is a secondary clock that is distributed to all regions. The purpose of the secondary clock
routing is to distribute the secondary clock sources to the secondary clock regions. Secondary clocks in the
LatticeECP3 devices are region-based resources. Certain EBR rows and special vertical routing channels bind the
secondary clock regions. This special vertical routing channel aligns with either the left edge of the center DSP
slice in the DSP row or the center of the DSP row. Figure 2-15 shows this special vertical routing channel and the
20 secondary clock regions for the LatticeECP3 family of devices. All devices in the LatticeECP3 family have eight
secondary clock resources per region (SC0 to SC7). The same secondary clock routing can be used for control
signals.
2-14
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