LFE3-95EA-7MG328I 查看數據表（PDF） - Lattice Semiconductor

零件编号

产品描述 (功能)

生产厂家

LFE3-95EA-7MG328I

LatticeECP3 Family Data Sheet Introduction

Lattice Semiconductor 

Architecture

LatticeECP3 Family Data Sheet

Edge Clock Sources

Edge clock resources can be driven from a variety of sources at the same edge. Edge clock resources can be

driven from adjacent edge clock PIOs, primary clock PIOs, PLLs, DLLs, Slave Delay and clock dividers as shown in

Figure 2-19.

Figure 2-19. Edge Clock Sources

Clock Input

From

Routing

Clock Input

From

Routing

Sources for top

edge clocks

From Routing

Clock

Input

Clock

Input

From Routing

DLL

Input

PLL

Input

Slave Delay

DLL

PLL

Sources for left edge clocks

Six Edge Clocks (ECLK)

Two Clocks per Edge

Slave Delay

DLL

PLL

From Routing

Clock

Input

Clock

Input

From Routing

DLL

Input

PLL

Input

Sources for right edge clocks

Notes:

1. Clock inputs can be configured in differential or single ended mode.

2. The two DLLs can also drive the two top edge clocks.

3. The top left and top right PLL can also drive the two top edge clocks.

Edge Clock Routing

LatticeECP3 devices have a number of high-speed edge clocks that are intended for use with the PIOs in the

implementation of high-speed interfaces. There are six edge clocks per device: two edge clocks on each of the top,

left, and right edges. Different PLL and DLL outputs are routed to the two muxes on the left and right sides of the

device. In addition, the CLKINDEL signal (generated from the DLL Slave Delay Line block) is routed to all the edge

clock muxes on the left and right sides of the device. Figure 2-20 shows the selection muxes for these clocks.

2-17

Share Link: