LFE3-35EA-8FTN256I 查看數據表（PDF） - Lattice Semiconductor
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LFE3-35EA-8FTN256I Datasheet PDF : 140 Pages
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Figure 2-20. Sources of Edge Clock (Left and Right Edges)
Architecture
LatticeECP3 Family Data Sheet
Input Pad
PLL Input Pad
DLL Output CLKOP
PLL Output CLKOS
PLL Output CLKOP
Routing
CLKINDEL
from DLL Slave Delay
Left and Right
Edge Clocks
ECLK1
7:1
Input Pad
PLL Input Pad
DLL Output CLKOS
PLL Output CLKOP
PLL Output CLKOS
Routing
CLKINDEL
from DLL Slave Delay
Figure 2-21. Sources of Edge Clock (Top Edge)
Input Pad
Top left PLL_CLKOP
Top Right PLL_CLKOS
Left DLL_CLKOP
Right DLL_CLKOS
Routing
CLKINDEL
(Left DLL_DEL)
Left and Right
Edge Clocks
ECLK2
7:1
ECLK1
7:1
Input Pad
Top Right PLL_CLKOP
Top Left PLL_CLKOS
Right DLL_CLKOP
Left DLL_CLKOS
Routing
CLKINDEL
(Right DLL_DEL)
ECLK2
7:1
The edge clocks have low injection delay and low skew. They are used to clock the I/O registers and thus are ideal
for creating I/O interfaces with a single clock signal and a wide data bus. They are also used for DDR Memory or
Generic DDR interfaces.
2-18
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