ATSAM3N1BA-AU 查看數據表（PDF） - Atmel Corporation

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ATSAM3N1BA-AU

ARM-based Flash MCU

Atmel Corporation 

SAM3N Summary

Figure 5-3.

Core Externally Supplied (backup battery)

ADC, DAC Supply

(3V-3.6V)

Backup

Battery +

-

Main Supply

IN

OUT

3.3V

LDO

ON/OFF

VDDIO

VDDIN

VDDOUT

VDDCORE

VDDPLL

I/Os.

ADC, DAC

Voltage

Regulator

PIOx (Output)

External wakeup signal

WAKEUPx

Note: The two diodes provide a “switchover circuit” (for illustration purpose)

between the backup battery and the main supply when the system is put in

backup mode.

5.4 Active Mode

Active mode is the normal running mode with the core clock running from the fast RC oscillator,

the main crystal oscillator or the PLL. The power management controller can be used to adapt

the frequency and to disable the peripheral clocks.

5.5 Low Power Modes

The various low-power modes of the SAM3N are described below:

5.5.1

Backup Mode

The purpose of backup mode is to achieve the lowest power consumption possible in a system

that is performing periodic wakeups to carry out tasks but not requiring fast startup time

(<0.1ms). Total current consumption is 3 µA typical.

The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz

oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The

regulator and the core supply are off.

Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.

The SAM3N can be awakened from this mode through WUP0-15 pins, the supply monitor (SM),

the RTT or RTC wake-up event.

Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con-

trol Register of the Cortex-M3 set to 1. (See the Power management description in The ARM

Cortex M3 Processor section of the product datasheet).

Exit from Backup mode happens if one of the following enable wake-up events occurs:

• WKUPEN0-15 pins (level transition, configurable debouncing)

19

11011BS–ATARM–22-Feb-12

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