ATSAMA5D41A-CU 查看數據表（PDF） - Atmel Corporation

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ATSAMA5D41A-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

4.7.3

External Bus Interface

16-bit wide interface, working at MCK/2, supporting:

 Static Memories

 NAND Flash with Multi-bit ECC

The EBI I/Os accept three drive level (LOW, MEDIUM, HIGH) allowing to avoid overshoots and give the best

performances according to the bus load and external memories voltage.

The drive levels are configured line by line with the LINEx field in the PIO I/O Drive Register x (PIO_DRIVER1 and

PIODRIVER2).

At reset, the selected drive is low. The user must make sure to program the correct drive according to the device

load.

4.8 I/O Drive Selection

The aim of this control is to adapt the signal drive to the frequency. The general purpose I/O lines can drive high

speed or low speed signals depending on the PIO multiplexing. To reduce the overshoots and improve the EMI

behavior, the I/Os feature a drive control which can be enabled in the PIO user interface. The PIO controller

embeds drive control registers. Two bits per I/O allow to select one drive from [High, Medium, Low] list.

SAMA5D4 Series [DATASHEET]

31

Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16

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