LR24C256D 查看數據表（PDF） - Leshan Radio Company,Ltd

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LR24C256D

128K bits (16,384 X 8) / 256K bits (32,768 X 8) Two-wire Serial EEPROM

Leshan Radio Company,Ltd 

LESHAN RADIO COMPANY, LTD.

DEVICE/PAGE ADDRESSES ( A1 and A0): The A1 and A0 pins are device address inputs that are hard wired for the

24C128 / 24 C256. Four 128k/256k devices may be addressed on a single bus system (device addressing is discussed in detail

under the Device Addressing section).

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed

with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock

data out of each device.

WRITE PROTECT (WP): The 24C128/ 24C256 has a Write Protect pin that provides hardware data protection. The Write

Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC,

the write protection feature is enabled and operates as shown in the following Table 2.

Functional Description

1. Memory Organization

24C128, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages of 64 bytes each.

Random word addressing requires a 14-bit data word address.

24C256, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each.

Random word addressing requires a 15-bit data word address.

2. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the

SDA pin may change only during SCL low time periods (see Figure 1). Data changes during SCL high periods will

indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any

other command (see Figure 2).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power mode (see Figure 2)

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.

STANDBY MODE: The LR24C128/LR24C256 features a low-power standby mode which is enabled: (a) upon

power-up and (b) after the receipt of the STOP bit and the completion of any internal operations

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by

following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

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