RT8120 查看數據表（PDF） - Richtek Technology
零件编号
产品描述 (功能)
生产厂家
RT8120 Datasheet PDF : 17 Pages
| |||
RT8120
especially when the height has a limitation. However, low
DCR and low profile inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which translates into the lower power loss.
However, the inductor current rising time increases with
inductance value. This means the transient response will
be slower. Therefore, the inductor design is a trade-off
between performance, size and cost.
In general, inductance is chosen such that the ripple
current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following
equation :
L(MIN) =
fSW
VIN − VOUT
x k x IOUT_RATED
x
VOUT
VIN
where k is the ratio between inductor ripple current and
rated output current.
Input Capacitor Selection
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Conservatively speaking,
an input capacitor should have a voltage rating 1.5 times
greater than the maximum input voltage to be considered
a safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
IRMS = IOUT x
VOUT
VIN
⎛
x ⎜1 −
⎝
VOUT
VIN
⎞
⎟
⎠
The next step is to select a proper capacitor for the RMS
current rating. Using more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a
capacitor bank is a good design. Placing the ceramic
capacitor close to the drain of the high side MOSFET can
also be helpful in reducing the input voltage ripple at
heavy load.
Output Capacitor Selection
The output capacitor and the inductor form a low-pass filter
in the buck topology. In steady state condition, the ripple
current flowing into/out of the capacitor results in voltage
ripple. The output voltage ripples contains two
components, ΔVOUT_ESR and ΔVOUT_C.
ΔVOUT_ESR = ΔIL x ESR
ΔVOUT_C
= ΔIL
x
1
8 x COUT
x fSW
When load transient occurs, the output capacitor supplies
the load current before controller can respond. Therefore,
the ESR will dominate the output voltage sag during load
transient. The output voltage sag can be calculated using
the following equation :
VOUT_SAG = ESR x ΔIOUT
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore ESL contributes to part of the voltage sag. Using
a capacitor with low ESL will obtain better transient
performance. Generally, using several capacitors
connected in parallel will also have better transient
performance than just one single capacitor with the same
total ESR.
Unlike electrolytic capacitors, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, it is
suggested to use a mixed combination of electrolytic
capacitor and ceramic capacitor for achieving better
transient performance.
MOSFET Selection
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high side MOSFET is small. Therefore, the switching
loss of the high side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such kind of application. However, the small duty cycle
means the low side MOSFET is on for most of the switching
cycle. Therefore, the conduction loss tends to dominate
the total power loss of the converter. To improve the overall
efficiency, MOSFETs with low RDS(ON) are preferred in the
circuit design. In some cases, more than one MOSFET
are connected in parallel to further decrease the on-state
Copyright ©2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS8120-08 September 2013
Share Link: 