M24C01-FBN6G 查看數據表（PDF） - STMicroelectronics

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M24C01-FBN6G

1-Kbit and 2-Kbit serial I²C bus EEPROMs

STMicroelectronics 

Instructions

M24C01/02-W M24C01/02-R M24C02-F

5.1.3

Minimizing Write delays by polling on ACK

The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC

parameters, but the typical time is shorter. To make use of this, a polling sequence can be

used by the bus master.

The sequence, as shown in Figure 7, is:

• Initial condition: a Write cycle is in progress.

• Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

• Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal Write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 7. Write cycle polling flowchart using ACK

Write cycle

in progress

Start condition

Device select

with RW = 0

First byte of instruction

with RW = 0 already

decoded by the device

NO ACK

returned

YES

Next

NO

Operation is

addressing the

memory

ReStart

YES

Send Address

and Receive ACK

Stop

NO

YES

StartCondition

Data for the

Write cperation

Continue the

Write operation

Device select

with RW = 1

Continue the

Random Read operation

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DocID024020 Rev 2

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