LPC1342FBD48 查看數據表（PDF） - NXP Semiconductors.

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LPC1342FBD48

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device

NXP Semiconductors. 

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.10 UART

The LPC1311/13/42/43 contains one UART.

Support for RS-485/9-bit mode allows both software address detection and automatic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

• Maximum UART data bit rate of 4.5 MBit/s.

• 16-byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.11 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. An additional SSP controller is

available on the LPC1313FBD48/01 package.

The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.11.1 Features

• Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC1311/13/42/43 contain one I2C-bus controller.

LPC1311_13_42_43

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 6 June 2012

© NXP B.V. 2012. All rights reserved.

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