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DAC1005D650HW/C1 查看數據表(PDF) - NXP Semiconductors.

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DAC1005D650HW/C1 Datasheet PDF : 42 Pages
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NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Table 5. Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = 40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate; PLL on;
unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ Max
Unit
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
IO(aux)
auxiliary output current differential outputs
VO(aux)
auxiliary output voltage compliance range
NDAC(aux)mono auxiliary DAC
monotonicity
guaranteed
I
-
2.2 -
mA
C
0
-
2
V
D
-
10 -
bit
Input timing (see Figure 10)
fdata
data rate
tw(CLK)
CLK pulse width
th(i)
input hold time
tsu(i)
input set-up time
Output timing
Dual-port mode input
C
-
-
160
MHz
C
1.5
-
Tdata 1.5 ns
C
1.1
-
-
ns
C
1.1
-
-
ns
fs
sampling frequency
C
ts
settling time
to ±0.5 LSB
D
NCO frequency range; fs = 640 Msps
fNCO
NCO frequency
register value = 00000000h
D
register value = FFFFFFFFh D
-
-
650
-
20 -
-
0
-
-
640 -
Msps
ns
MHz
MHz
fstep
step frequency
D
Low-power NCO frequency range; fDAC = 640 MHz
fNCO
NCO frequency
register value = 00000000h
D
register value = F8000000h
D
-
0.149 -
-
0
-
-
620 -
Hz
MHz
MHz
fstep
step frequency
Dynamic performance; PLL on
D
-
20 -
MHz
SFDR
spurious-free dynamic fdata = 80 MHz; fs = 320 Msps;
range
B = fdata / 2
fo = 35 MHz at 0 dBFS
C
-
82 -
dBc
fdata = 80 MHz; fs = 640 Msps;
B = fdata / 2
fo = 4 MHz at 0 dBFS
I
-
76 -
dBc
fo = 19 MHz at 0 dBFS
I
-
75 -
dBc
fdata = 160 MHz; fs = 640 Msps;
B = fdata / 2
fo = 70 MHz at 0 dBFS
C
-
82 -
dBc
DAC1005D650
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 September 2010
© NXP B.V. 2010. All rights reserved.
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