T2080 查看數據表（PDF） - Freescale Semiconductor
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T2080 Datasheet PDF : 29 Pages
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Chip features
Should the packet remain unclassified, the traffic is retried with an error in the case of Type 10 and 11 traffic and dropped in
the case of Type 9 traffic. Dropped traffic is logged and upon a threshold can assert an error interrupt.
Classification allows Type 9, 10 and 11 traffic to be distributed across 64 possible Frame queues. A single dedicated inbound
Type 8 Port-write Frame queue is provided. For all outbound traffic types (Type 8, 9, 10 and 11), the Data Path Acceleration
Architecture allows a very large number of outbound Frame queues effectively limited by system, software and performance
constraints.
The RMan is DPAA entity designed to work in conjunction with the chip's Serial RapidIO controllers. This figure illustrates
RMan use cases.
Figure 5. RMan use cases
Inbound Serial RapidIO traffic, including messages (Type 11), doorbells (Type 10), and data (Type 9) are classified by the
RMan and enqueued to a configured FQ, allowing the DPAA to deliver the "data" to any DPAA consumer, including vCPUs,
accelerators, or Ethernet ports (FMan). Outbound traffic enqueued to the RMan for transmission is given a configured ID,
allowing the target FQ on the receiving device to be identified. The RMan/Serial RapidIO combination is particularly useful
for chip-to-chip communication, with an x4 Serial RapidIO interface providing up to 16 Gbps of data/message bandwidth
between RMan enabled QorIQ chips.
4.10.2.6 SEC 5.2
The SEC 5.2 can perform full protocol processing for the following security protocols:
• IPsec
• SSL/TLS
• 3GPP RLC encryption/decryption
• LTE PDCP
• SRTP
• IEEE 802.1AE MACSec
• IEEE 802.16e WiMax MAC layer
The SEC 5.2 supports the following algorithms, modes, and key lengths as raw modes, or in combination with the security
protocol processing described above.
T2080 Product Brief, Rev 0, 04/2014
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Freescale Semiconductor, Inc.
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