MC146818AS 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

生产厂家

MC146818AS

REAL-TIME CLOCK PLUS RAM

Motorola => Freescale 

SIGNAL DESCRIPTIONS

ADO-AD7 – MULTIPLEXED BIDIRECTIONAL

ADDRESSIDATA BUS

The block diagram in Figure 1, shows the pin connection

with the major internal functions of the MC146818A Real-

Time Clock plus RAM. The following paragraphs describe

the function of each pin.

VDD, VSS

DC power is provided to the part on these two pins, VDD

being the more positive voltage. The minimum and maxi-

mum voltages are listed in the Electrical Characteristics

tables.

Multiplexed bus processors save pins by presenting the

address during the first portion of the bus cycle and using

the same pins during the second portion for data. Address-

then-data multiplexing does not slow the access time of the

MC146818A since the bus reversal from address to data is

occurring during the internal RAM access time.

\\;~,;.

>..t..,,,..,.$)

The address must be valid just prior to the fall ,@#~$~~LE

at which time the M C146818A latches the addr.e~ ??@ ADO

to AD5, Valid write data must be presente@t~~~~fi8?d stable

during the latter portion of the DS or ~~~~?~~. In a read

MOT–MOTEL

The MOT pin offers flexibility when choosing bus type,

When tied to VDD, Motorola timing is used. When tied to

VSS, competitor timing is used. The MOT pin must be hard-

wired to the VDD or VSS supply and cannot be switched

during operation of the MC146818A.

OSC1, OSC2 – TIME BASE, INPUTS

The time base for the time functions may be an external

signal or the crystal oscillator. External square waves at

4.184304 MHz, 1.M576 MHz, or 32.768 kHz may be con-

nected to OSCI as shown in Figure 9. The internal time-base

frequency to be used is chosen in Register A.

cycle, the M C146818A outputs eight ~[~bf~~ta during the

latter portion of the DS or ~ pulse~$~$~mases driving the

bus (returns the output drivers to t~,h,$h-impedance state)

when DS falls in the Motorola&cJ&e o~~OTEL or R~ rises in

the other case.

..,~.?t)?;~,

AS – MULTIPLEX~:~+@,tp#:~=S,yS,t\>

STROBE, INPUT

A positive goin~+ mu~~[pjexed address strobe pulse serves

to demultiplex t~~x,~~s. The falling edge of AS or ALE causes

the address+~:$~~atched within the MC146818A.

,!:!~ ‘,\$$v<.,,,:hi:.

DS ~ #&$A’”sTROBE OR READ, INPUT

The on-chip oscillator is designed for a parallel resonant

~~,DS pin has two interpretations via the MOTEL circuit,

AT cut crystal at4.1 M04 MHz, 1.048576 MHz or32.768 kHz

frequencies. The crystal connections are shown in Figure 10

and the crystal characteristics in Figure 11.

CKOUT – CLOCK OUT, OUTPUT

The CKOUT pin is an output at the time-base freque~~

divided by 1 or 4. A major use for CKOUT is as the t~u~:t,

clock to the microprocessor; thereby saving the c,@$:&::@

second crystal. The frequency of CKOUT depends%~okt$he

,:&$$n@manating from a Motorola type processor, DS is a

.,,,%~o$$lve pulse during the latter portion of the bus cycle, and

.!.,-.,,,::*:~.J~+&,.>$,a<rTio,usly called DS (data strobe), E (enable), and 42 (42

*a:J clock). During read cycles, DS signifies the time that the

~\33, ‘ RTC is to drive the bidirectional bus. In write cycles, the trail-

ing edge of DS causes the Real-Time Clock plus RAM to

latch the written data,

The second MOTEL interpretation of DS is that of ~,

MEM R, or ~ emanating from the competitor type pro-

..j:.+.k’~

CKFS – CLOCK OUT FREQUENCY #%&<$: INPUT

cessor. In this case, DS identifies the time period when the

real-time clock plus RAM drives the bus with read data. This

interpretation of DS is also the same as an output-enable

signal on a typical memory.

When the CKFS pin is tied to VD~$~$:jcai~es CKOUT to be

the same frequency as the time b~e ~~fie OSCI pin. When

CKFS is tied to Vss, CKOUJ:~~l~@~OSCl time-base fre-

quency divided by four. T~le~~ summarizes the effect

,,: .,,

~me Base,,~~~~=~k Frequency

(oscl~, ;$t~,‘;+ Select Hn

Freq~ ~,,,,, ‘“

(CKFS)

4.ly3~,,Myz

,.,..r“

4.W:

M HZ

High

Low

~$+&6 MHZ

High

‘:\:~576 M HZ

Low

Clock Frequency

Output Hn

(CKOUT)

4.1943W MHz

1.W576 MHz

1.W576 MHz

262.144 kHz

R/~ – READ/WRITE, INPUT

The MOTEL circuit treats the R/~ pin in one of two ways.

When a Motorola type processor is connected, R/~ is a

level which indicates whether the current cycle is a read or

write. A read cycle is indicated with a high level on R/~

while DS is high, whereas a write cycle is a Iowon R/~ dur-

ing DS.

-

The second interpretation of R/~ is as a negative write

pulse, ~R, MEMW, and l/OW from competitor tv~e ~ro-

cessors, The MOTEL circuit in t~s mode gives R/~’pin” the

same meaning as the write (W) pulse on many generic

RAMs.

‘32.768 kHz

32.7& kHz

High

Low

32.768 kHz

8.192 kHz

SQW – SQUARE WAVE, OUTPUT

The SQW Din can output a signal from one of the 15 taps

provided by ihe 22 internal-divid~r stages. The frequency of

the SQW may be altered by programming Register A, as

shown in Table 5. The SQW signal may be turned on and off

using the SQWE bit in Register B.

~S – CHIP SELECT, INPUT

The chip-select (C~) signal must be asserted (low) for a

bus cycle in which the MC146818A is to be accessed. C= is

not latched and must be stable during DS and AS (Motorola

case of MOTEL) and during ~D and ~R. Bus cycles which

—

take place without asserting C= cause no actions to take

place within the MC146818A. When C% is not used, it should

be grounded. (See Figure 20).

M070ROLA

@

Semiconductor Products Inc.

8

Share Link: