BD82HM55-SLGZS 查看數據表（PDF） - Intel
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BD82HM55-SLGZS Datasheet PDF : 956 Pages
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5.29
5.28.1
5.28.2
5.28.3
IInntteell®®
VT-d
VT-d
Support for
Chipset and
Objectives .......................................................................
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280
280
281
5.28.4 Virtualization Support for PCH’s IOxAPIC .............................................. 281
5In.2te8l.®5
5
Virtualization
Series Chipset
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Precision Event Timer (HPET)...................
Series Chipset Platform Clocks..................
281
282
5.29.1 Platform Clocking Requirements .......................................................... 282
6
Ballout Definition................................................................................................... 283
6.1 PCH Desktop Ballout ........................................................................................ 283
6.2 PCH Ballout Mobile Ballout ................................................................................ 294
6.3 PCH Ballout Small Form Factor Ballout ............................................................... 306
7
Package Information ............................................................................................. 319
7.1 PCH package (Desktop Only) ............................................................................ 319
7.2 PCH package (Mobile Only)............................................................................... 321
7.3 PCH package (Mobile SFF Only)......................................................................... 323
8
Electrical Characteristics ....................................................................................... 325
8.1 Thermal Specifications ..................................................................................... 325
8.1.1
Desktop Storage Specifications and Thermal Design Power (TDP) ............ 325
8.1.2
Mobile Storage Specifications and Thermal Design Power (TDP) ............... 325
8.2
8.3
AInbtseol®lut5e
Maximum and
Series Chipset
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326
327
8.4 General DC Characteristics ............................................................................... 327
8.5 Display DC Characteristics ................................................................................ 340
8.6 AC Characteristics ........................................................................................... 342
8.7 Power Sequencing and Reset Signal Timings ....................................................... 360
8.8 Power Management Timing Diagrams................................................................. 363
8.9 AC Timing Diagrams ........................................................................................ 366
9
Register and Memory Mapping............................................................................... 377
9.1 PCI Devices and Functions................................................................................ 378
9.2 PCI Configuration Map ..................................................................................... 379
9.3 I/O Map ......................................................................................................... 379
9.3.1
Fixed I/O Address Ranges .................................................................. 379
9.3.2
Variable I/O Decode Ranges ............................................................... 382
9.4 Memory Map................................................................................................... 383
9.4.1
Boot-Block Update Scheme................................................................. 385
10 Chipset Configuration Registers............................................................................. 387
10.1 Chipset Configuration Registers (Memory Space) ................................................. 387
10.1.1 V0CTL—Virtual Channel 0 Resource Control Register .............................. 390
10.1.2 V0STS—Virtual Channel 0 Resource Status Register ............................... 390
10.1.3 V1CTL—Virtual Channel 1 Resource Control Register .............................. 391
10.1.4 V1STS—Virtual Channel 1 Resource Status Register ............................... 391
10.1.5 CIR0—Chipset Initialization Register 0.................................................. 391
10.1.6 CIR1—Chipset Initialization Register 1.................................................. 392
10.1.7 REC—Root Error Command Register .................................................... 392
10.1.8 ILCL—Internal Link Capabilities List Register ......................................... 392
10.1.9 LCAP—Link Capabilities Register .......................................................... 393
10.1.10 LCTL—Link Control Register ................................................................ 393
10.1.11 LSTS—Link Status Register................................................................. 394
10.1.12 BCR—Backbone Configuration Register................................................. 394
10.1.13 RPC—Root Port Configuration Register ................................................. 394
10.1.14 DMIC—DMI Control Register ............................................................... 396
10.1.15 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports Register .............................................................. 396
10.1.16 FLRSTAT—FLR Pending Status Register ................................................ 397
10.1.17 CIR5—Chipset Initialization Register 5.................................................. 398
10.1.18 TRSR—Trap Status Register................................................................ 398
10.1.19 TRCR—Trapped Cycle Register ............................................................ 398
10.1.20 TWDR—Trapped Write Data Register.................................................... 399
10.1.21 IOTRn—I/O Trap Register (0–3) .......................................................... 399
10.1.22 DMC—DMI Miscellaneous Control Register ............................................ 400
10.1.23 CIR6—Chipset Initialization Register 6.................................................. 400
10.1.24 DMC2—DMI Miscellaneous Control Register 2 ........................................ 400
Datasheet
9
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