C5002 查看數據表（PDF） - Cypress Semiconductor
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C5002 Datasheet PDF : 16 Pages
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C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Crystal and Reference Oscillator Parameters
Characteristic
Symbol Min
Typ
Max
Units Conditions
Frequency
Fo
12.00 14.31818
16.00
MHz
Tolerance
TC
-
-
+/-100
PPM Calibration Note 1
TS
-
-
+/- 100
PPM Stability (Ta -10 to +60C) Note 1
TA
-
-
5
PPM Aging (first year @ 25C) Note 1
Mode
OM
-
-
-
Parallel Resonant
Pin Capacitance
CP
32
pF Capacitance of XIN and Xout pins to
ground (each)
DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Startup time
Ts
-
-
30
µS
Load Capacitance
CL
-
16
-
pF See calculation section below
Effective Series
R1
-
-
resistance (ESR)
40
Ohms
Power Dissipation
DL
-
-
0.10
mW Note 1
Shunt Capacitance CO
-
--
8
pF Crystal’s internal package
capacitance (total)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
= 2.0 pF
Clock generator internal pin capacitance of 32 pF, Load to the crystal is therefore = 16.0 pF
The total capacitance see by the crystal would therefore be
= 18.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07014 Rev. **
5/04/2001
Page 11 of 16
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