RT9045GSP 查看數據表（PDF） - Richtek Technology
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RT9045GSP Datasheet PDF : 12 Pages
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RT9045
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9045. A low ESR capacitor larger than 20μF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between the RT9045 and
the proceeding power converter.
Thermal Consideration
RT9045 regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed absolute maximum
operation junction temperature of 125°C. The power
dissipation definition in device is :
PD = (VIN − VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
TJ(MAX) is the maximum operation junction temperature
125°C, TA is the ambient temperature and the θJA is the
junction to ambient thermal resistance. The junction to
ambient thermal resistance for SOP-8 (Exposed Pad)
package is 86°C/W on the standard JEDEC 51-7 (4 layers,
2S2P) thermal test board. The maximum power dissipation
at TA = 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (86°C/W) = 1.163W
Figure 9 shows the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As shown in Figure 10, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the SOP-8 (Exposed Pad) package.
www.richtek.com
10
Ambient
Molding Compound
Gold Line
Lead Frame
PCB
Die Pad
Case (Exposed Pad)
Figure 9. SOP-8 (Exposed Pad) Package Sectional
Drawing
RGOLD-LINE RLEAD FRAME RPCB
path 1
Junction
RDIE RDIE-ATTACH RDIE-PAD
RPCB
path 2
Case
(Exposed Pad)
Ambient
RMOLDING-COMPOUND
path 3
Figure 10. Thermal Resistance Equivalent Circuit
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80
Copper Area (mm2)
Figure 11. Relation Between Thermal Resistance θJA and
Copper Area
Figure 11 shows the relation between thermal resistance
θJA and copper area on a standard JEDEC 51-7 (4 layers,
2S2P) thermal test board at TA = 25°C. We have to consider
the copper couldn't stretch infinitely and avoid the tin
overflow. We use the “Dog-Bone” copper patterns on the
top layer as shown in Figure 12.
DS9045-04 August 2011
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