FSA839UCX 查看數據表（PDF） - Fairchild Semiconductor
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FSA839UCX Datasheet PDF : 10 Pages
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Test Diagrams
VCC
VBn
B0 or B1
A
S
GND
VOUT
RL
CL
50 35pF
Control
VCC
50%
Input
0V
tR = tF = 2.5ns
Switch
Output
VOUT
0V
0.9 x VOUT
tON
tOFF
0.9 x VOUT
CL includes fixture and stray capacitance.
Logic input waveforms inverted for switches
that have the opposite logic sense.
Figure 4. Turn On / Off Timing
VBn
Control
Input
VCC
B0
A
B1
S
GND
VOUT
Control
Input
VCC
0V
RL
CL
50
35pF
VOUT
CL includes fixture and stray capacitance.
50%
tR = tF = 2.5ns
0.9 x VOUT
TD
Figure 5. Break-Before-Make Timing
VCC 10nF
0 or VCC
50
S
VCC
A
BO
B1
GND
VIN
VOUT
Network
Analyzer
50
50
MEAS
50
REF
50
OFF-ISOLATION
=
20log
VOUT
VIN
ON-LOSS
=
20log
VOUT
VIN
CROSSTALK
=
20log
VOUT
VIN
Figure 6. Off Isolation and Crosstalk
© 2008 Fairchild Semiconductor Corporation
FSA839 • Rev. 1.0.0
7
www.fairchildsemi.com
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