ADDS-21160M-EZLITE 查看數據表（PDF） - Analog Devices

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ADDS-21160M-EZLITE

1 MSPS 16-/14-Bit Analog I/O Port

Analog Devices 

AD15700

ADC PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic

Type Description

H10

DGND_ADC

P

H12

D[8] or SDOUT

DO

H11

D[9] or SCLK

DI/O

G12

D[10] or SYNC

DO

G11

D[11] or RDERROR DO

F12, F11, D[12:15]

DO

E12, E11

G10

BUSY

DO

G9

DGND_ADC

P

E10

RD

DI

K10

CS_ADC

DI

D12

RESET

DI

K9

PD

DI

E7

CNVST

DI

H8

AGND_ADC

P

G5

REF

AI

H5

REFGND

AI

J7

INGND

P

J5, K5, INA, INB,

AI

L5, M5 INC, IND

Digital Power Ground

When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data

output synchronized to SCLK. Conversion results are stored in an on-chip register.

The ADC provides the conversion result, MSB first, from its internal shift register.

The DATA format is determined by the logic level of OB/2C. In Serial Mode, when

EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when

EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge

and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on

SCLK falling edge and valid on the next rising edge.

When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a serial

data clock input or output, dependent upon the logic state of the EXT/INT pin. The

active edge where the data SDOUT is updated depends upon the logic state of the

INVSCLK pin.

When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital

output frame synchronization for use with the internal data clock (EXT/INT = Logic

LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH

and remains HIGH while SDOUT output is valid. When a read sequence is initiated

and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output

is valid.

When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial

Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started

and not complete when the following conversion is complete, the current data is lost

and RDERROR is pulsed high.

Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH,

these outputs are in high impedance.

Busy Output. Transitions HIGH when a conversion is started, and remains HIGH

until the conversion is complete and the data is latched into the on-chip shift register.

The falling edge of BUSY could be used as a data ready clock signal.

Must be Tied to Digital Ground

Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled.

Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled. CS_ADC is also used to gate the external serial clock.

Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.

Power-Down Input. When set to a logic HIGH, power consumption is reduced and

conversions are inhibited after the current one is completed.

Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold

state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW),

if CNVST is held low when the acquisition phase (t8) is complete, the internal

sample/hold is put into the hold state and a conversion is immediately started.

Must be Tied to Analog Ground

Reference Input Voltage

Reference Input Analog Ground

Analog Input Ground

Analog Inputs. Refer to Table I for input range configuration.

–12–

REV. A

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