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BD9397EFV Datasheet PDF : 30 Pages
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BD9397EFV
Datasheet
●3.4.6 Maximum DCDC output voltage(Vout ,Max)
The DCDC output maximum voltage is restricted by Max Duty of N output.
Moreover, the voltage needed in order that Vf may modulate by LED current also with the same number of LEDs.
Vf becomes high, so that there is generally much current.
When you have grasped the variation factor of everythings, such as variation in a DCDC input voltage range, the variation
and temperature characteristics of LED load, and external parts, please carry out a margin setup.
●3.4.7 Setting the OVP
In BD9397EFV, when over voltage in VOUT line is detected,
the instant stop of the N pin output is carried out, and
voltage rise operation is stopped. But the latch stop by CP
charge is not performed. If VOUT drops by naturally
discharge, it is less than the hysteresis voltage of OVP
detection and the oscillation condition is fulfilled, N output
will be resumed again.
○Equation of setting OVP detect
VOVP 2.43 R1 R2 [V ]
R2
N pin output is suspended at the time of SCP detection, it
stops step-up operation, and the latch protection by CP
timer.
VOUT
OVP
200k
FB
ERR AMP -
400k
LED_LV
+
+
OVP COMP - 2.43V
SCP COMP -
+ 0.2V
R1
R2
REG9V=9V
○Equation of setting SCP detect
VSCP 0.2 R1 R2 [V ]
R2
Figure 20.
Moreover, there is an OVPFB function which returns OVP voltage and controls error amplifier so that output voltage may be
raised, even when there is no PWM signal during a soft start.
○The VOUT setting formula by OVPFB in Soft Start
VOUT
3
2
R1 R2
R2
R1
400
VLED _
LV
[V ]
●3.4.8 FAIL Logic
FAIL signal output pin (OPEN DRAIN); when an abnormality is detected, NMOS is brought into GND Level.
The rating of this pin is 36V.
State
In normal state, In STB
In completion of an abnormality, when the
UVLO is detected(after CP latch)
FAIL output
OPEN
GND Level
(500ohm typ.)
●3.4.9 How to set the UVLO
UVLO pin detect the power supply voltage: Vin for step-up DC/DC converters.
Operation starts operation on more than 2.5V (typ.) and Operation stops on less
than 2.4V (typ.) .
Since internal impedance exists in UVLO pin, cautions are needed for selection of
resistance for resistance division.
A Vin voltage level to make it detecting becomes settled like the following formula
by resistance division of R1 and R2 (unit: kΩ).
○Equation of setting UVLO release
Zin= 610 kΩ
(typ.)
1400k 530k
125k 480k
Vin
R1
UVLO
R2
1000pF
VinDET
2.5
R1 R2
R2
1400k1125k
530k
1
480k
R1
[V ]
AGND AGND
○ Equation of setting UVLO lock
Figure 21.
Vinlock
2.4
R1
R2
R2
1
1400k 125k
530k
1
480k
40k
R1
[V ]
*Also including the variation in IC, please also take the part variation in a set into consideration for an actual constant setup,
and inquire enough to it.
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