AD9211-170EB 查看數據表（PDF） - Analog Devices

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AD9211-170EB

10-Bit, 170/200/250 MSPS 1.8 V A/D Converter

Analog Devices 

Preliminary Technical Data

10µF

1.25Vp-p

49.9Ω

0.1µF

R

AVDD

VIN+

AD9211

VIN-

CML

AGND

0.1uF

Figure 10. Single-Ended Input Configuration using SPI enabled CML function

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9211 the sample clock inputs

(CLK+ and CLK-) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK- pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias (See Figure X).

AVDD

AD9211

150Ω

PECL

AD9512

0.1uF

150Ω

0.1uF

CLK+

AD9230

CLK-

Figure X. Differential PECL Sample Clock for AD9230/AD9211

CLK+

2pF

1.2V

CLK-

2pF

Figure .Equivalent Clock Input Circuit

Figure X shows one preferred method for clocking the AD9211.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD9211 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9211 while preserving the

fast rise and fall times of the signal, which are critical to a low

jitter performance.

Clock

Source

CLK+

AD9230

CLK-

Figure X. Transformer Coupled Differential Clock for AD9230/AD9211

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure X. The AD9512 (or same family) from offers excellent

jitter performance.

Rev. PrA | Page 15 of 21

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