MAX17036 查看數據表（PDF） - Maxim Integrated
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MAX17036 Datasheet PDF : 38 Pages
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1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PIN
NAME
FUNCTION
This low-voltage logic input indicates power usage and sets the operating mode together
with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when PSI is forced high.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
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PSI
irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by
connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVR PSI
MODE
1
0
0
X
0
1
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency according to the following equation:
fSW = 1/(CTON x (RTON + 6.5k))
16
TON
where CTON = 16.26pF.
The external resistor must also satisfy the requirement [VIN(MIN)/RTON] 10µA where VIN(MIN) is
the minimum VIN value expected in the application.
TON is high impedance in shutdown.
Clock Enable CMOS Push-Pull Logic Output Powered by V3P3. This inverted logic output indicates
when the output voltage sensed at FB is in regulation. CLKEN is forced high in shutdown and during
soft-start and soft-stop transitions. CLKEN is forced low during dynamic VID transitions and for an
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CLKEN
additional 20µs after the transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms
PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The
CLKEN upper threshold is blanked during any downward output-voltage transition that happens when
the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes
high if FB is within the PWRGD threshold window.
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PWRGD
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high
impedance whenever the slew-rate controller is active (output-voltage transitions), and continues
to be forced high impedance for an additional 20µs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that
happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled
internal-transition-related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-
mode driver IC. DRSKP swings from VDD to GND. When DRSKP is high, the driver ICs operate in
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DRSKP forced-PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and
operate in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence,
instructing the external drivers to shut down.
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