STM32F103C6 查看數據表（PDF） - STMicroelectronics

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STM32F103C6

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces

STMicroelectronics 

STM32F103xx

Description

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is

monitored for failure. During such a scenario, it is disabled and software interrupt

management follows. Similarly, full interrupt management of the PLL clock entry is available

when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the High Speed APB

(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and

the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low

Speed APB domain is 36 MHz.

Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using the USART.

Power supply schemes

● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

● VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

and PLL. In VDD range (ADC is limited at 2.4 V).

● VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

Power supply supervisor

The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It

is always active, and ensures proper operation starting from/down to 2 V. The device

remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need

for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD power supply and compares it to the VPVD threshold. An interrupt can be generated

when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The

interrupt service routine can then generate a warning message and/or put the MCU into a

safe state. The PVD is enabled by software.

Refer to Table 9: Embedded reset and power control block characteristics for the values of

VPOR/PDR and VPVD.

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