78F0547 查看數據表（PDF） - NEC => Renesas Technology
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78F0547 Datasheet PDF : 663 Pages
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APPENDIX D REVISION HISTORY
(7/7)
Page
Description
CHAPTER 27 FLASH MEMORY
p. 581
Addition of Caution to Figure 27-1 Format of Internal Memory Size Switching Register (IMS)
p. 582
Addition of Caution to Figure 27-2 Format of Internal Expansion RAM Size Switching Register (IXS)
p. 583
Modification of pin numbers in Table 27-3 Wiring Between 78K0/KF2 and Dedicated Flash Programmer
p. 584
Modification of wiring of pins 1, 2, and 11 in Figure 27-3 Example of Wiring Adapter for Flash Memory
Writing in 3-Wire Serial I/O (CSI10) Mode
p. 585
Modification of wiring of pins 1, 2, and 11 in Figure 27-4 Example of Wiring Adapter for Flash Memory
Writing in UART (UART6) Mode
pp. 586, 587
Modification of transfer rate in (1) CSI10 and (2) UART6 in 27.5
p. 592
Modification of transfer rate in Speed column of Table 27-7 Communication Modes
p. 594
Addition of 27.8 Security Settings
p. 598
Modification of 27.9.1 Boot swap function
CHAPTER 28 ON-CHIP DEBUG FUNCTION (µPD78F0547D ONLY)
p. 600
Revision of chapter
CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET)
p. 615
Revision of chapter
CHAPTER 31 PACKAGE DRAWINGS
pp. 635, 636
Addition of package drawing
CHAPTER 32 CAUTIONS FOR WAIT
p. 638
Modification of <Conditions for maximum/minimum number of wait clocks> of A/D converter in Table 32-1
Registers That Generate Wait and Number of CPU Wait Clocks
p. 639
Modification of number of wait clocks in Table 32-2 RAM Accesses That Generate Wait and Number of
CPU Wait Clocks
APPENDIX A DEVELOPMENT TOOLS
p. 642
Addition of (2) When using the on-chip debug emulator QB-78K0MINI to Figure A-1 Development Tool
Configuration
p. 645
Addition of A.5.2 When using on-chip debug emulator QB-78K0MINI
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
p. 647
Addition of chapter
APPENDIX D REVISION HISTORY
p. 657
Addition of chapter
Preliminary User’s Manual U17397EJ2V1UD
663
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