EVAL-AD1939AZ 查看數據表（PDF） - Analog Devices

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EVAL-AD1939AZ

8-Channel DAC with PLL and Differential Outputs, 192 kHz, 24 Bits

Analog Devices 

Data Sheet

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTERS (DACs)

The AD1933 DAC channels are arranged as differential,

four stereo pairs giving eight analog outputs for minimum

external components. The DACs include on-board digital

reconstruction filters with 70 dB stop-band attenuation and

linear phase response, operating at an oversampling ratio of

4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each

channel has its own independently programmable attenuator,

adjustable in 255 steps in increments of 0.375 dB. Digital inputs

are supplied through four serial data input pins (one for each

stereo pair) and a common frame clock (DLRCLK) and bit

clock (DBCLK). Alternatively, one of the TDM modes can be

used to access up to 16 channels on a single TDM data line.

Each output pin has a nominal common-mode dc level of 1.5 V

and swings ±1.27 V for a 0 dBFS digital input signal. A third-

order, external, low-pass filter is recommended to remove high

frequency noise present on the output pins. The use of op amps

with low slew rates or low bandwidths can cause high frequency

noise and tones to fold down into the audio band; therefore,

exercise care in selecting these components.

The voltage at CM, the common-mode reference pin, can be

used to bias the external op amps that buffer the output signals

(see the Power Supply and Voltage Reference section).

CLOCK SIGNALS

The on-chip, phase-locked loop (PLL) can be selected to

reference the input sample rate from either of the LRCLK pins

or 256, 384, 512, or 768 times the sample rate, referenced to the

48 kHz mode from the MCLKI/XI pin. The default at power-up

is 256 × fS from MCLKI/XI pin. In 96 kHz mode, the master

clock frequency stays at the same absolute frequency; therefore,

the actual multiplication rate is divided by 2. In 192 kHz mode,

the actual multiplication rate is divided by 4. For example, if a

device in the AD1933 family is programmed in 256 × fS mode, the

frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.

If the AD1933 is then switched to 96 kHz operation (by writing

to the SPI port), the frequency of the master clock should

remain at 12.288 MHz, which becomes 128 × fS. In 192 kHz

mode, this becomes 64 × fS.

The internal clock for the DACs varies by mode: 512 × fS (48 kHz

mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By

default, the on-board PLL generates this internal master clock

from an external clock. A direct 512 × fS (referenced to 48 kHz

mode) master clock can be used for DACs if selected in the PLL

and Clock Control 1 register.

AD1933

The PLL can be powered down in the PLL and Clock Control 0

register. To ensure reliable locking when changing PLL modes,

or if the reference clock is unstable at power-on, power down

the PLL and power it back up when the reference clock has

stabilized.

The internal master clock can be disabled in the PLL and Clock

Control 0 register to reduce power dissipation when the AD1933

is idle. The clock should be stable before it is enabled. Unless a

standalone mode is selected (see the Serial Control Port section),

the clock is disabled by reset and must be enabled by writing to

the SPI port for normal operation.

To maintain the highest performance possible, limit the clock

jitter of the internal master clock signal to less than a 300 ps rms

time interval error (TIE). Even at these levels, extra noise or

tones can appear in the DAC outputs if the jitter spectrum

contains large spectral peaks. If the internal PLL is not used, it

is highly recommended that an independent crystal oscillator

generate the master clock. In addition, it is especially important

that the clock signal not be passed through an FPGA, CPLD, or

other large digital chip (such as a DSP) before being applied to

the AD1933. In most cases, this induces clock jitter due to the

sharing of common power and ground connections with other

unrelated digital output signals. When the PLL is used, jitter in

the reference clock is attenuated above a certain frequency

depending on the loop filter.

RESET AND POWER-DOWN

The function of the RST pin sets all the control registers to their

default settings. To avoid pops, reset does not power down the

analog outputs. After RST is deasserted, and the PLL acquires

lock condition, an initialization routine runs inside the

AD1933. This initialization lasts for approximately 256 master

clock cycles.

The power-down bits in the PLL and Clock Control 0 and DAC

Control 1 registers power down the respective sections. All

other register settings are retained. To guarantee proper startup,

the RST pin should be pulled low by an external resistor.

Rev. E | Page 11 of 28

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