K4B4G1646Q 查看數據表（PDF） - Samsung

零件编号

产品描述 (功能)

生产厂家

K4B4G1646Q

4Gb Q-die DDR3L SDRAM Olny x16 96FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.35V

Samsung 

K4B4G1646Q

datasheet

Preliminary Rev. 0.5

DDR3L SDRAM

NOTE :Clock and Strobe are drawn on a different time scale.

tIS

tIH

CK

CK

DQS

DQS

VDDQ

tDS tDH

VIH(AC) min

VIH(DC) min

dc to VREF

region

VREF(DC)

dc to VREF

region

VIL(DC) max

tangent

line

VIL(AC) max

tIS tIH

tDS tDH

nominal

line

tangent

line

nominal

line

VSS

 TR

 TF

Hold Slew Rate

Rising Signal

=

tangent line [ VREF(DC) - VIL(DC)max ]

 TR

Hold Slew Rate

Falling Signal

=

tangent line [ VIH(DC)min - VREF(DC) ]

 TF

Figure 27. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH

(for ADD/CMD with respect to clock)

- 65 -

Share Link: