Memory ICs
(3) Timing chart
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
CS
tCSS
SK
tDIS
DI
DO (READ)
DO (WRITE)
tSKH
tDIH
tPD0
tSKL
tPD1
STATUS VALID
tCSH
tDF
tDF
• Data is acquired from DI in synchronization with the SK rise.
• During a reading operation, data is output from DO in synchronization with the SK rise.
• During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of
a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
• After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig. 1 Synchronized data timing
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