LTC1417(RevA) 查看數據表（PDF） - Linear Technology
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LTC1417 Datasheet PDF : 32 Pages
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LTC1417
APPLICATIONS INFORMATION
Unipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
11a and 11b show the extra components required for full-
scale error adjustment. Zero offset is achieved by adjust-
ing the offset applied to the AIN– input. For zero offset
error, apply 125µV (i.e., 0.5LSB) at the input and adjust
the offset at the AIN– input until the output code flickers
between 0000 0000 0000 00 and 0000 0000 0000 01. For
full-scale adjustment, an input voltage of 4.095625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
OFFSET R1
ADJ 50k
ANALOG INPUT
R8
100Ω
R3
R4
24k
100Ω
R5 FS R2
47k ADJ 50k
R6
24k
10µF
0.1µF
R7
48k
5V
1 AIN+ VDD
2 AIN–
3
LTC1417
VREF
4 REFCOMP
5 AGND VSS
1417 F11a
Figure 11a. Offset and Full-Scale Adjust Circuit
If – 5V Is Not Available
–5V
OFFSET R1
ADJ 50k
ANALOG INPUT
R3
R4
24k
100Ω
R5 FS R2
47k ADJ 50k
R6
24k
10µF
0.1µF
5V
1 AIN+ VDD
2 AIN–
3
LTC1417
VREF
4 REFCOMP
5 AGND VSS
–5V
1417 F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
If – 5V Is Available
14
Bipolar Offset and Full-Scale Error Adjustment
Bipolar offset and full-scale errors are adjusted in a
similar fashion to the unipolar case using the circuit in
Figure 11b. Again, bipolar offset error must be adjusted
before full-scale error. Bipolar offset error adjustment is
achieved by adjusting the offset applied to the AIN– input.
For zero offset error, apply – 125µV (i.e., – 0.5LSB) at AIN+
and adjust the offset at the AIN– input until the output code
flickers between 0000 0000 0000 00 and 1111 1111 1111
11. For full-scale adjustment, an input voltage of 2.047625V
(FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
To obtain the best performance from the LTC1417, a
printed circuit board with ground plane is required. The
ground plane under the ADC area should be as free of
breaks and holes as possible, such that a low impedance
path between all ADC grounds and all ADC decoupling
capacitors is provided. It is critical to prevent digital noise
from being coupled to the analog input, reference or
analog power supply lines. Layout should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 10 (DGND) and all other analog
grounds should be connected to this single analog ground
plane. The REFCOMP bypass capacitor and the VDD by-
pass capacitor should also be connected to this analog
ground plane. No other digital grounds should be con-
nected to this analog ground plane. Low impedance ana-
log and digital power supply common returns are essential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
sn1417 1417fas
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