100329 查看數據表（PDF） - Fairchild Semiconductor

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100329

Low Power Octal ECL/TTL Bidirectional Translator with Register

Fairchild Semiconductor 

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Functional Diagram

Pin Descriptions

Pin Names

Description

E0–E7

T0–T7

OE

ECL Data I/O

TTL Data I/O

Output Enable Input

CP

Clock Pulse Input (Active Rising Edge)

DIR

Direction Control Input

All pins function at 100K ECL levels except for T0–T7.

Truth Table

OE DIR CP

ECL

Port

TTL

Port

Notes

L L X Input Z (Note 1)(Note 3)

L H X LOW Input (Note 2)(Note 3)

H

H

L

L

(Cut-Off)

L

H

L

H

(Note 1)

(Note 1)

H

H

H

L

H

H

L

X

L

H

NC (Note 1)(Note 3)

L

(Note 2)

H

(Note 2)

HHL

NC

X (Note 2)(Note 3)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

Z = High Impedance

= LOW-to-HIGH Clock Transition

NC = No Change

Note 1: ECL input to TTL output mode.

Note 2: TTL input to ECL output mode.

Note 3: Retains data present before CP.

Note: DIR and OE use ECL logic levels

Detail

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