IDT72200L50TPB 查看數據表（PDF） - Integrated Device Technology

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IDT72200L50TPB

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™

64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8

tCLKH

tCLKL

WCLK

WEN

tENS

tENH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AE

RCLK

Empty+7

tSKEW2(1)

tAE

Empty+8

tENS

tAE

(2)

tENH

REN

2680 drw 11

NOTES:

1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the curent clock cycle. If the time between

the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty - 6 words in the FIFO when AE goes LOW.

Figure 9. Almost Empty Flag Timing

5.12

14

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