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EP3C80

Cyclone III Device Handbook

Altera Corporation 

Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family

2–5

Logic Array Blocks

■ LAB control signals

■ LE carry chains

■ Register chains

■ Local interconnect

The local interconnect transfers signals between LEs in the same LAB. Register chain

connections transfer the output of one LE register to the adjacent LE register in a LAB.

The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing

the use of local and register chain connections for performance and area efficiency.

Figure 2–4 shows the LAB structure for the Cyclone III device family.

Figure 2–4. Cyclone III Device Family LAB Structure

Row Interconnect

Column

Interconnect

Direct link

interconnect

from adjacent

block

Direct link

interconnect

from adjacent

block

Direct link

interconnect

to adjacent

block

Direct link

interconnect

to adjacent

block

LAB

Local Interconnect

LAB Interconnects

The LAB local interconnect is driven by column and row interconnects and LE

outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM

blocks, and embedded multipliers from the left and right can also drive the local

interconnect of a LAB through the direct link connection. The direct link connection

feature minimizes the use of row and column interconnects, providing higher

performance and flexibility. Each LE can drive up to 48 LEs through fast local and

direct link interconnects.

December 2011 Altera Corporation

Cyclone III Device Handbook

Volume 1

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