A54SX08A-FPQ208 查看數據表（PDF） - Actel Corporation

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A54SX08A-FPQ208

SX-A Family FPGAs

Actel Corporation 

SX-A Family FPGAs

Power Dissipation

A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during

operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature,

the operating current, and the system's ability to dissipate heat.

A complete power evaluation should be performed early in the design process to help identify potential heat-related

problems in the system and to prevent the system from exceeding the device’s maximum allowed junction

temperature.

The actual power dissipated by most applications is significantly lower than the power the package can dissipate.

However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps:

1. Estimate the power consumption of the application.

2. Calculate the maximum power allowed for the device and package.

3. Compare the estimated power and maximum power values.

Estimating Power Dissipation

The total power dissipation for the SX-A family is the sum of the DC power dissipation and the AC power dissipation:

PTotal = PDC + PAC

EQ 2-5

DC Power Dissipation

The power due to standby current is typically a small component of the overall power. An estimation of DC power

dissipation under typical conditions is given by:

PDC = IStandby * VCCA

EQ 2-6

Note: For other combinations of temperature and voltage settings, refer to the eX, SX-A and RT54SX-S Power

Calculator.

AC Power Dissipation

The power dissipation of the SX-A family is usually dominated by the dynamic power dissipation. Dynamic power

dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is

defined as follows:

or:

PAC =

PAC = PC-cells + PR-cells + PCLKA + PCLKB + PHCLK + POutput Buffer + PInput Buffer

EQ 2-7

VCCA2 * [(m * CEQCM * fm)C-cells + (m * CEQSM * fm)R-cells + (n * CEQI * fn)Input Buffer + (p * (CEQO + CL) * fp)Output Buffer

+ (0.5 * (q1 * CEQCR * fq1) + (r1 * fq1))CLKA + (0.5 * (q2 * CEQCR * fq2)+ (r2 * fq2))CLKB + (0.5 * (s1 * CEQHV * fs1) +

(CEQHF * fs1))HCLK]

EQ 2-8

2-8

v5.3

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