STM32F301C6T6 查看數據表（PDF） - STMicroelectronics

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STM32F301C6T6

ARM® Cortex®-M4 32-bit MCU+FPU, up to 64 KB Flash, 16 KB SRAM, ADC, DAC, COMP, Op-Amp, 2.0 – 3.6 V

STMicroelectronics 

STM32F301x6 STM32F301x8

Functional overview

3.8

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

3.9

Direct memory access (DMA)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-

memory and memory-to-peripheral transfers. The DMA controller supports circular buffer

management, avoiding the generation of interrupts when the controller reaches the end of

the buffer.

Each of the 7 DMA channels is connected to dedicated hardware DMA requests, with

software trigger support for each channel. Configuration is done by software and transfer

sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, timers, DAC and ADC.

3.10

3.10.1

Interrupts and events

Nested vectored interrupt controller (NVIC)

The STM32F301x6/8 devices embed a nested vectored interrupt controller (NVIC) able to

handle up to 60 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

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