V385
8-BIT LVDS TRANSMITTER FOR VIDEO
AC Timing Diagrams
TxCLK IN
TxIN
TCIP
TCIL
TCIH
TCIH
THTC
Figure AC1. Transmitter Setup/Hold and High/Low Times (Falling Edge Strobe or R_FB=0)
TxCLK IN
TxCLK OUT+
TCCD
TxCLK OUT-
Figure AC2. Clock IN to Clock OUT Delay (Rising Edge Strobe or R_FB=1)
PWRDWN#
VCC
TxCLK IN
Figure AC3. Phase Lock Loop Set Time
TPLLS
Unknown
V385 Datasheet
6
3/30/05
Revision 1.6
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com