S25FL127SABMFI003 查看數據表（PDF） - Cypress Semiconductor
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S25FL127SABMFI003 Datasheet PDF : 142 Pages
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S25FL127S
5.3.2
Separate RESET# Input Initiated Hardware (Warm) Reset
When the RESET# input transitions from VIH to VIL for > tRP the device will reset register states in the same manner as power-on
reset but, does not go through the full reset process that is performed during POR. The hardware reset process requires a period of
tRPH to complete. If the POR process did not complete correctly for any reason during power-up (tPU), RESET# going low will initiate
the full POR process instead of the hardware reset process and will require tPU to complete the POR process.
A separate RESET# input is available only in the SOIC16 and BGA package options. The RESET# input has an internal pull-up to
VCC and should be left unconnected if not used. The RESET command is independent of the state of RESET#. If RESET# is high or
unconnected, and the RESET instruction is issued, the device will perform software reset.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any operation in progress,
makes all outputs high impedance, and ignores all read/write commands for the duration of tRPH. The device resets the
interface to standby state.
If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted low again after
tRH.
Table 11. Hardware Reset Parameters
Parameter
Description
Limit
Time
Unit
tRS
Reset Setup -Prior Reset end and RESET# high before RESET#
low
Min
50
ns
tRPH
tRP
tRP
tRH
Reset Pulse Hold - RESET# low to CS# low
RESET# Pulse Width
RESET# Pulse Width (only when AutoBoot enabled)
Reset Hold - RESET# high before CS# low
Min
35
µs
Min
200
ns
Max
5
µs
Min
50
ns
Notes:
1. RESET# Low is ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine when CS#
may go Low.
2. Sum of tRP and tRH must be equal to or greater than tRPH.
RESET#
CS#
Figure 25. Separate RESET# Input Initiated Hardware Reset
tRP
Any prior reset
tRH
tRH
tRPH
tRS
tRPH
Document Number: 001-98282 Rev. *I
Page 32 of 142
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