ICS9148F-49 查看數據表（PDF） - Integrated Circuit Systems
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ICS9148F-49 Datasheet PDF : 9 Pages
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ICS9148-49
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7,8,10,11
9
12
13
14
15
16
17
18
19
20
21
22,23,24
26
25
27
28
PIN NAME
GND1
X1
X2
GND2
PCICLK_E
PCICLK_F
PCICLK (0:3)
VDD2
PCICLK_4
SEL100/66.6#
VDD3
48MHz
GND3
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
GND
VDDLC
CPUCLK (2:0)
IOAPIC
VDDLA
VDD1
REF0
TYPE
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
OUT
IN
PWR
OUT
PWR
IN
IN
IN
IN
PWR
PWR
OUT
OUT
PWR
PWR
OUT
DESCRIPTION
Ground for REF outputs, X1, X2.
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Early PCICLK. Leads PCICLK (0:4,_F) by 2ns ±250ps. Not
affected by PCI_STOP#
Free Running PCI output. oNot affected by PCI_STOP#
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
PCI clock output. TTL compatible 3.3V
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Power for 48MHz
Fixed CLK output @ 48MHz
Ground for 48MHz
Turns on Spread Spctrum when active. 0.5% down spread.1
Powers down chip. Internal PLLs, all output are turned off.
Halt CPUCLK (2:0) at logic "0" level when input is low.
Halts PCICLK (0:4) at logic "0" level when input low. Does
not affect PCICLK_E 7 PCICLK_F
Ground for PLL core
Power for CPU outputs, nominally 2.5V
CPU and Host clock outputs nominally 2.5V
IOAPIC clock output 14.318MHz.
Power for IOAPIC
Power for REF outputs.
14.318MHz clock output/Latched input at power up.
2
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