MFRC522_(2007) 查看數據表（PDF） - NXP Semiconductors.

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MFRC522_
(Rev.:2007)

Contactless Reader IC

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Contactless Reader IC

33. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . 3

Table 2: Ordering information . . . . . . . . . . . . . . . . . 4

Table 3: Pin description . . . . . . . . . . . . . . . . . . . . . . 7

Table 4: Communication overview for ISO/IEC

14443A/MIFARE® reader/writer . . . . . . . . 9

Table 5: MFRC522 Registers Overview . . . . . . . . 11

Table 6: Behavior of Register Bits and its Designation

13

Table 7: Reserved register (address 00h); reset

value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8: Description of Reserved register bits . . . . 13

Table 9: CommandReg register (address 01h); reset

value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 10: Description of CommandReg bits. . . . . . . 14

Table 11: CommIEnReg register (address 02h); reset

value: 80h. . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 12: Description of CommIEnReg bits . . . . . . . 14

Table 13: DivIEnReg register (address 03h); reset

value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 14: Description of DivIEnReg bits. . . . . . . . . . 16

Table 15: CommIRqReg register (address 04h); reset

value: 14h. . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 16: Description of CommIRqReg bits . . . . . . 16

Table 17: DivIRqReg register (address 05h); reset

value: X0h . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 18: Description of DivIRqReg bits . . . . . . . . . 17

Table 19: ErrorReg register (address 06h); reset

value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 20: Description of ErrorReg bits . . . . . . . . . . . 18

Table 21: Status1Reg register (address 07h); reset

value: 21h. . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 22: Description of Status1Reg bits . . . . . . . . . 19

Table 23: Status2Reg register (address 08h); reset

value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 24: Description of Status2Reg bits . . . . . . . . . 20

Table 25: FIFODataReg register (address 09h); reset

value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 26: Description ofFIFODataReg bits. . . . . . . . 21

Table 27: FIFOLevelReg register (address 0Ah); reset

value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 28: Description of FIFOLevelReg bits . . . . . . 21

Table 29: WaterLevelReg register (address 0Bh);

reset value: 08h . . . . . . . . . . . . . . . . . . . . 21

Table 30: Description of WaterLevelReg bits . . . . . . 22

Table 31: ControlReg register (address 0Ch); reset

value: 10h. . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 32: Description of ControlReg bits . . . . . . . . . 22

Table 33: BitFramingReg register (address 0Dh); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 34: Description of BitFramingReg bits . . . . . . 23

Table 35: CollReg register (address 0Eh); reset value:

XXh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 36: Description of CollReg bits. . . . . . . . . . . . 23

Table 37: Reserved register (address 0Fh); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 38: Description of Reserved register bits . . . . 24

Table 39: Reserved register (address 10h); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 40: Description of Reserved register bits . . . . 24

Table 41: ModeReg register (address 11h); reset

value: 3Fh . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 42: Description of ModeReg bits . . . . . . . . . . 25

Table 43: TxModeReg register (address 12h); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 44: Description of TxModeReg bits . . . . . . . . 26

Table 45: RxModeReg register (address 13h); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 46: Description of RxModeReg bits . . . . . . . . 26

Table 47: TxControlReg register (address 14h); reset

value: 80h . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 48: Description of TxControlReg bits . . . . . . . 27

Table 49: TxAutoReg register (address 15h); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 50: Description of TxAutoReg bits . . . . . . . . . 28

Table 51: TxSelReg register (address 16h); reset

value: 10h . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 52: Description of TxSelReg bits . . . . . . . . . . 28

Table 53: RxSelReg register (address 17h); reset

value: 84h . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 54: Description of RxSelReg bits . . . . . . . . . . 29

Table 55: RxThresholdReg register (address 18h);

reset value: 84h . . . . . . . . . . . . . . . . . . . . 30

Table 56: Description of RxThresholdReg bits. . . . . 30

Table 57: DemodReg register (address 19h); reset

value: 4Dh . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 58: Description of DemodReg bits . . . . . . . . . 30

Table 59: Reserved register (address 1Ah); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 60: Description of Reserved register bits . . . . 31

Table 61: Reserved register (address 1Bh); reset

value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 62: Description of Reserved register bits . . . . 31

Table 63: MfTxReg register (address 1Ch); reset value:

62h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

continued >>

112132

Product data sheet

Rev. 3.2 — 22 May 2007

© NXP B.V. 2007. All rights reserved.

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