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MFRC522_(2007) 查看數據表(PDF) - NXP Semiconductors.

零件编号
产品描述 (功能)
生产厂家
MFRC522_
(Rev.:2007)
NXP
NXP Semiconductors. NXP
MFRC522_ Datasheet PDF : 109 Pages
First Prev 101 102 103 104 105 106 107 108 109
NXP Semiconductors
MFRC522
Contactless Reader IC
10.2.4 Address byte . . . . . . . . . . . . . . . . . . . . . . . 48
10.3 UART Interface . . . . . . . . . . . . . . . . . . . . . 48
10.3.1 Connection to a host . . . . . . . . . . . . . . . . . 48
10.3.2 Selection of the transfer speeds . . . . . . . . 49
10.3.3 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . 52
10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.4.2 Data validity. . . . . . . . . . . . . . . . . . . . . . . . 53
10.4.3 START and STOP conditions . . . . . . . . . . 53
10.4.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 54
10.4.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . 54
10.4.6 7-BIT ADDRESSING. . . . . . . . . . . . . . . . . 55
10.4.7 Register Write Access . . . . . . . . . . . . . . . 56
10.4.8 Register Read Access. . . . . . . . . . . . . . . . 57
10.4.9 HS mode . . . . . . . . . . . . . . . . . . . . . . . . . 58
10.4.10High Speed Transfer . . . . . . . . . . . . . . . . . 58
10.4.11 Serial Data transfer Format in HS mode . . 58
10.4.12Switching from F/S to HS mode and Vice Versa
60
10.4.13MFRC522 at Lower Speed modes . . . . . . 60
11 Analog Interface and Contactless UART. . 61
11.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.2 TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.3 Serial Data Switch . . . . . . . . . . . . . . . . . . 63
11.4 MFIN/MFOUT interface support . . . . . . . . 63
11.5 CRC co-processor. . . . . . . . . . . . . . . . . . . 64
12 FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.2 Accessing the FIFO Buffer . . . . . . . . . . . . 65
12.3 Controlling the FIFO-Buffer . . . . . . . . . . . . 65
12.4 Status Information about the FIFO-Buffer . 65
13 Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . 67
14 Interrupt Request System . . . . . . . . . . . . . 68
15 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . 69
16 Power Reduction modes . . . . . . . . . . . . . . 70
16.1 Hard Power-down . . . . . . . . . . . . . . . . . . . 70
16.2 Soft Power-down . . . . . . . . . . . . . . . . . . . . 70
16.3 Transmitter Power-down . . . . . . . . . . . . . . 70
17 Reset and Oscillator Startup Time . . . . . . 71
17.1 Reset Timing Requirements . . . . . . . . . . . 71
17.2 Oscillator Startup Time . . . . . . . . . . . . . . . 71
18
MFRC522 Command Set . . . . . . . . . . . . . 72
18.1 General Description . . . . . . . . . . . . . . . . . 72
18.2 General Behavior . . . . . . . . . . . . . . . . . . . 72
18.3 MFRC522 Commands Overview . . . . . . . 72
18.3.1 MFRC522 Command Description . . . . . . . 73
18.3.1.1Idle Command . . . . . . . . . . . . . . . . . . . . . 73
18.3.1.2Mem Command . . . . . . . . . . . . . . . . . . . . 73
18.3.1.3Generate RandomID Command . . . . . . . 73
18.3.1.4CalcCRC Command. . . . . . . . . . . . . . . . . 73
18.3.1.5Transmit Command . . . . . . . . . . . . . . . . . 73
18.3.1.6NoCmdChange Command . . . . . . . . . . . 73
18.3.1.7Receive Command. . . . . . . . . . . . . . . . . . 74
18.3.1.8Transceive Command . . . . . . . . . . . . . . . 74
18.3.1.9MFAuthent Command . . . . . . . . . . . . . . . 74
18.3.1.10SoftReset Command . . . . . . . . . . . . . . . 75
19 Testsignals . . . . . . . . . . . . . . . . . . . . . . . . 76
19.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
19.2 Test bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 76
19.3 Testsignals at pin AUX . . . . . . . . . . . . . . . 77
19.3.1 Example: Output TestDAC 1 on AUX1 and
TestDAC 2 on AUX2 . . . . . . . . . . . . . . . . . 79
19.3.2 Example: Output Testsignal Corr1 on AUX1
and MinLevel on AUX2 . . . . . . . . . . . . . . . 79
19.3.3 Example: Output ADC channel I on AUX 1 and
ADC channel Q on AUX 2. . . . . . . . . . . . . 80
19.3.4 Example: Output RxActive on AUX 1 and
TxActive on AUX 2 . . . . . . . . . . . . . . . . . . 81
19.3.5 Example: Output Rx Data Stream on AUX 1
and AUX 2. . . . . . . . . . . . . . . . . . . . . . . . . 82
19.4 PRBS (Pseudo-Random Binary Sequence) 82
20 Limiting values . . . . . . . . . . . . . . . . . . . . . 83
21 Recommended operating conditions . . . . 83
22 Thermal characteristics. . . . . . . . . . . . . . . 83
23 Characteristics . . . . . . . . . . . . . . . . . . . . . 84
23.1 Input Pin Characteristics . . . . . . . . . . . . . . 84
23.1.1 Input Pin characteristics for pins EA, I2C and
NRESET . . . . . . . . . . . . . . . . . . . . . . . . . . 84
23.1.2 Input Pin characteristics for pin MFIN . . . . 84
23.1.3 Input/Output Pin characteristics for pins D1,
D2, D3, D4, D5, D6 and D7 . . . . . . . . . . . 84
23.1.4 Input Pin characteristics for pin SDA . . . . 84
23.1.5 Output Pin characteristics for Pin MFOUT 85
23.1.6 Output Pin characteristics for Pin IRQ . . . 85
23.1.7 Input Pin characteristics for Pin Rx . . . . . . 85
23.1.8 Input Pin characteristics for pin OSCIN . . 85
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: sales.addresses@www.nxp.com
Date of release: 22 May 2007
Document identifier: 112132

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