MFRC52201HN1/TRAYBM_10 查看數據表（PDF） - NXP Semiconductors.

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MFRC52201HN1/TRAYBM_10

Contactless reader IC

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Contactless reader IC

25. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. Communication overview for

ISO/IEC 14443 A/MIFARE reader/writer . . . . . .7

Table 5. Connection protocol for detecting different

interface types . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 6. MOSI and MISO byte order . . . . . . . . . . . . . . . .9

Table 7. MOSI and MISO byte order . . . . . . . . . . . . . . .10

Table 8. Address byte 0 register; address MOSI . . . . . .10

Table 9. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . . 11

Table 10. Selectable UART transfer speeds . . . . . . . . . . 11

Table 11. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 12. Read data byte order . . . . . . . . . . . . . . . . . . . .12

Table 13. Write data byte order . . . . . . . . . . . . . . . . . . . .13

Table 14. Address byte 0 register; address MOSI . . . . . .15

Table 15. Register and bit settings controlling the signal

on pin TX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 16. Register and bit settings controlling the signal

on pin TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 17. CRC coprocessor parameters . . . . . . . . . . . . .27

Table 18. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29

Table 19. Behavior of register bits and their designation .33

Table 20. MFRC522 register overview . . . . . . . . . . . . . .34

Table 21. Reserved register (address 00h); reset value:

00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .36

Table 22. Reserved register bit descriptions . . . . . . . . . .36

Table 23. CommandReg register (address 01h);

reset value: 20h bit allocation . . . . . . . . . . . . .36

Table 24. CommandReg register bit descriptions . . . . . .36

Table 25. ComIEnReg register (address 02h);

reset value: 80h bit allocation . . . . . . . . . . . . .36

Table 26. ComIEnReg register bit descriptions . . . . . . . .37

Table 27. DivIEnReg register (address 03h);

reset value: 00h bit allocation . . . . . . . . . . . . .37

Table 28. DivIEnReg register bit descriptions . . . . . . . . .37

Table 29. ComIrqReg register (address 04h);

reset value: 14h bit allocation . . . . . . . . . . . . .37

Table 30. ComIrqReg register bit descriptions . . . . . . . .38

Table 31. DivIrqReg register (address 05h);

reset value: x0h bit allocation . . . . . . . . . . . . .38

Table 32. DivIrqReg register bit descriptions . . . . . . . . . .38

Table 33. ErrorReg register (address 06h);

reset value: 00h bit allocation . . . . . . . . . . . . .39

Table 34. ErrorReg register bit descriptions . . . . . . . . . .39

Table 35. Status1Reg register (address 07h);

reset value: 21h bit allocation . . . . . . . . . . . . .40

Table 36. Status1Reg register bit descriptions . . . . . . . .40

Table 37. Status2Reg register (address 08h);

reset value: 00h bit allocation . . . . . . . . . . . . . 41

Table 38. Status2Reg register bit descriptions . . . . . . . . 41

Table 39. FIFODataReg register (address 09h);

reset value: xxh bit allocation . . . . . . . . . . . . . 42

Table 40. FIFODataReg register bit descriptions . . . . . . 42

Table 41. FIFOLevelReg register (address 0Ah);

reset value: 00h bit allocation . . . . . . . . . . . . . 42

Table 42. FIFOLevelReg register bit descriptions . . . . . . 42

Table 43. WaterLevelReg register (address 0Bh);

reset value: 08h bit allocation . . . . . . . . . . . . . 42

Table 44. WaterLevelReg register bit descriptions . . . . . 43

Table 45. ControlReg register (address 0Ch);

reset value: 10h bit allocation . . . . . . . . . . . . . 43

Table 46. ControlReg register bit descriptions . . . . . . . . 43

Table 47. BitFramingReg register (address 0Dh);

reset value: 00h bit allocation . . . . . . . . . . . . . 44

Table 48. BitFramingReg register bit descriptions . . . . . 44

Table 49. CollReg register (address 0Eh);

reset value: xxh bit allocation . . . . . . . . . . . . . 44

Table 50. CollReg register bit descriptions . . . . . . . . . . . 44

Table 51. Reserved register (address 0Fh);

reset value: 00h bit allocation . . . . . . . . . . . . . 45

Table 52. Reserved register bit descriptions . . . . . . . . . . 45

Table 53. Reserved register (address 10h);

reset value: 00h bit allocation . . . . . . . . . . . . . 45

Table 54. Reserved register bit descriptions . . . . . . . . . . 45

Table 55. ModeReg register (address 11h);

reset value: 3Fh bit allocation . . . . . . . . . . . . . 46

Table 56. ModeReg register bit descriptions . . . . . . . . . 46

Table 57. TxModeReg register (address 12h);

reset value: 00h bit allocation . . . . . . . . . . . . . 46

Table 58. TxModeReg register bit descriptions . . . . . . . 47

Table 59. RxModeReg register (address 13h);

reset value: 00h bit allocation . . . . . . . . . . . . . 47

Table 60. RxModeReg register bit descriptions . . . . . . . 47

Table 61. TxControlReg register (address 14h);

reset value: 80h bit allocation . . . . . . . . . . . . . 48

Table 62. TxControlReg register bit descriptions . . . . . . 48

Table 63. TxASKReg register (address 15h);

reset value: 00h bit allocation . . . . . . . . . . . . . 49

Table 64. TxASKReg register bit descriptions . . . . . . . . 49

Table 65. TxSelReg register (address 16h);

reset value: 10h bit allocation . . . . . . . . . . . . . 49

Table 66. TxSelReg register bit descriptions . . . . . . . . . 49

Table 67. RxSelReg register (address 17h);

reset value: 84h bit allocation . . . . . . . . . . . . . 50

Table 68. RxSelReg register bit descriptions . . . . . . . . . 50

continued >>

MFRC522_34

Product data sheet

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All information provided in this document is subject to legal disclaimers.

Rev. 3.4 — 5 March 2010

112134

© NXP B.V. 2010. All rights reserved.

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