AD7476BRTZ-R2 查看數據表（PDF） - Analog Devices
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AD7476BRTZ-R2 Datasheet PDF : 24 Pages
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AD7476/AD7477/AD7478
SERIAL INTERFACE
Figure 23, Figure 24, and Figure 25 show the detailed timing
diagrams for serial interfacing to the AD7476, AD7477, and
AD7478, respectively. The serial clock provides the conversion
clock and controls the transfer of information from the part
during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input at
this point. The conversion initiates and requires 16 SCLK cycles
to complete. Once 13 SCLK falling edges have elapsed, the
track-and-hold goes back into track on the next SCLK rising
edge as shown at Point B in Figure 23, Figure 24, and Figure 25.
On the sixteenth SCLK falling edge, the SDATA line will go
back into three-state. If the rising edge of CS occurs before
16 SCLKs have elapsed, the conversion terminates and the
SDATA line goes back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge as shown in
Figure 23, Figure 24, and Figure 25.
CS
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476/
AD7477/AD7478.
CS going low provides the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having clocked out on the previous (15th)
falling edge. In applications with a slower SCLK, it is possible to
read data on each SCLK rising edge, although the first leading
zero has to be read on the first SCLK falling edge after the CS
falling edge. Therefore, the first rising edge of SCLK after the
CS falling edge provides the second leading zero. The 15th
rising SCLK edge has DB0 provided or the final zero for the
AD7477 and AD7478. This may not work with most
microcontrollers/DSPs, but could possibly be used with FPGAs
and ASICs.
t1
SCLK
tCONVERT
t2
t6
1
2
3
4
5
t3
t4
t7
THREE-
STATE
SDATA
Z
ZERO
ZERO
ZERO
DB11
DB10
4 LEADING ZEROS
B
13
14
15
16
t5
DB2
DB1
t8
DB0
THREE-STATE
tQUIET
Figure 23. AD7476 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
15
16
THREE-
STATE
SDATA
t3
t4
t7
t5
t8
Z ZERO ZERO ZERO
DB9
DB8
THREE-STATE
DB0
ZERO
ZERO
4 LEADING ZEROS
2 TRAILING ZEROS
Figure 24. AD7477 Serial Interface Timing Diagram
tQUIET
t1
CS
SCLK
tCONVERT
t2
t6
B
1
2
3
4
12
13
14
15
16
t3
t4
THREE-
SDATA STATE Z ZERO ZERO ZERO
DB7
t7
t5
ZERO ZERO
ZERO
t8
ZERO
THREE-STATE
tQUIET
4 LEADING ZEROS
8 BITS OF DATA
4 TRAILING ZEROS
Figure 25. AD7478 Serial Interface Timing Diagram
Rev. F | Page 18 of 24
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